Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 793

15.5.3.5.9 MII Management Control Register (MIIMCON)
MIIMCON, shown in
Offset eTSEC1:0x2_452C
0
R
W
Reset
Table 15-48 describes the fields of the MIIMCON register.
Bits Name
0–15 — Reserved
16–31 PHY Control If written, an MII Mgmt write cycle is performed using this 16-bit data, the pre-configured PHY address
(at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register Address]). Its default
value is 0x0000.
15.5.3.5.10 MII Management Status Register (MIIMSTAT)
The MIIMSTAT register is read only by the user.
register.
O
Offset eTSEC1:0x2_4530
0
R
W
Reset
Table 15-49 describes the fields of the MIIMSTAT register.
Bits Name
0–15 — Reserved
16–31 PHY Status Following an MII Mgmt read cycle, the 16-bit data can be read from this location. Its default value is
0x0000.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Figure 15-44, is written by the user.
—
Figure 15-44. MII Mgmt Control Register Definition
Table 15-48. MIIMCON Field Descriptions
—
Figure 15-45. MIIMSTAT Register Definition
Table 15-49. MIIMSTAT Field Descriptions
Enhanced Three-Speed Ethernet Controllers
15 16
All zeros
Description
Figure 15-45 describes the definition for the MIIMSTAT
15 16
All zeros
Description
Access: WO
PHY Control
Access: Read only
PHY Status
31
31
15-75