Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 580

DMA/Messaging Unit
Example: Big-endian mode descriptor's data structure. Note that the descriptor structure must be aligned
on an 8-word boundary.
struct {
double a;
double b;
double c;
double d;
} Descriptor;
Results: Source Address = 0x44332211 <MSB..LSB>
Destination Address = 0x88776655 <MSB..LSB>
Next Descriptor Address = 0x21436587 <MSB..LSB>
Byte Count = 0x67452301 <MSB..LSB>
12.4.4.2 Descriptor in Little-Endian Mode
In little-endian mode, each segment descriptor should be programmed in descending significant-byte
order.
Example: Little-endian mode descriptor's data structure. Note that the descriptor structure must be
aligned on an 8-word boundary.
struct {
double a;
double b;
double c;
double d;
} Descriptor;
Results: Source Address = 0x44332211 <MSB..LSB>
Destination Address = 0x88776655 <MSB..LSB>
Next Descriptor Address = 0x12345678 <MSB..LSB>
Byte Count = 0x76543210 <MSB..LSB>
12.5 Initialization/Application Information
12.5.1 Initialization Steps in Direct Mode
The initialization steps of a DMA transfer in direct mode are described as follows:
1. Poll the CB (channel busy) bit in the DMA status register (DMASRn) to make sure the DMA
channel is idle.
2. Initialize the DMASARn, DMADARn, and the DMABCRn.
3. Initialize DMAMRn[CTM]) to indicate direct mode. Other control parameters in the mode register
can also be initialized here if necessary.
4. First clear then set the DMAMRn[CS] to start the DMA transfer.
12.5.2 Initialization Steps in Chaining Mode
The initialization steps of a DMA transfer in chaining mode are described as follows:
1. Build a chain of descriptor segments in memory. Refer to
Descriptors."
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
12-20
/* 0x1122334455667788 double word*/
/* 0x55667788aabbccdd double word*/
/* 0x8765432101234567 double word */
/* 0x0123456789abcdef double word */
/* 0x8877665544332211 double word*/
/* 0x1122334488776655 double word*/
/* 0x7654321012345678 double word */
/* 0x0123456776543210 double word */
Section 12.4.4, "DMA Segment
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