Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 266

System Configuration
5.7.5.2 Global Timers Mode Registers (GTMDR1–GTMDR4)
The global timers mode registers (GTMDR1, GTMDR2, GTMDR3, and GTMDR4) are shown in
Figure 5-42.
Erratic behavior may occur if GTCFR1 and GTCFR2 are not initialized before the GTMDRn. Only
GTCFRn[RSTn] and GTCFRn[STPn] can be modified at any time.
Offset 0x10(GTMDR1)
0x12(GTMDR2)
0
R
W
Reset
Figure 5-42. Global Timers Mode Registers (GTMDR1
Table 5-59 defines the bit fields of GTMDR.
Bits Name
0–7 SPS Secondary prescaler value
The secondary prescaler is programmed to divide the clock input to corresponding timer by values from 1 to
256. The value 0x00 divides the clock by 1 and 0xFF divides the clock by 256.
8–9 CE Capture edge and enable interrupt
00 Disable interrupt on capture event; capture function is disabled
01 Capture on rising TIN n edge only and enable interrupt on capture event.
10 Capture on falling TIN n edge only and enable interrupt on capture event.
11 Capture on any TIN n edge and enable interrupt on capture event.
Note: The frequency of TIN n should be slower than system clock (TIN n is sampled internally by system clock
to detect TIN n 's rising/falling edge before updating the counter)
10 OM Output mode
0 Toggle TOUT n every time when the corresponding timer matches its reference value.
1 Active-low pulse on TOUT n for one timer input clock cycle (4 input clock cycles for the system clock) as
defined by the ICLK n bits. Thus, TOUT n may be low for four general system clocks, one general system
slow go clock period, or one TIN n pin clock cycle period.
Note: TOUT n changes are internally synchronized to the rising edge of the system clock
11 ORI Output reference interrupt enable
0 Disable interrupt for reference reached (does not affect interrupt on capture function).
1 Enable interrupt on reaching the reference value.
12 FRR Free run/restart mode
0 Free run. The timer count continues to increment after the reference value is reached.
1 Restart. The timer count is reset immediately after the reference value is reached.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-58
0x20(GTMDR3)
0x22(GTMDR4)
SPS
Table 5-59. GTMDR Bit Settings
7 8 9 10
CE OM
All zeros
–
GTMDR4)
Description
Access: Read/Write
11 12 13 14
ORI FRR ICLK
Freescale Semiconductor
15
GE