Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 935

Offset
0x2_31CA– Reserved
0x2_31D4
0x2_3400 SNOOP1—Snoop 1
0x2_3404 SNOOP2—Snoop 2
0x2_3408 AGE_CNT_THRESH—Age count threshold
0x2_340C PRI_CTRL—Priority control
0x2_3410 SI_CTRL—System interface control
0x2_3500 CONTROL—Control
0x2_3504– Reserved, should be cleared
0x2_3FFF
1
This register has separate functions for the host and device operation; the host function is listed first in the table.
The following sections provide details about the registers in the USB memory map.
Memory may be viewed from either a big-endian or little-endian byte
ordering perspective depending on the processor configuration. In
big-endian mode, the most-significant byte of word 0 is located at address 0
and the least-significant byte of word 0 is located at address 3. In
little-endian mode, the least-significant byte of word 0 is located at address
0 and the most-significant byte of word 0 is located at address 3. Within
registers, bits are numbered within a word starting with bit 31 as the
most-significant bit. By convention USB registers use little-endian byte
ordering. In the USB DR module, these are the registers from offsets 0x00
to 0x1FF. The registers associated with the internal system interface (0x400
and above) use big-endian byte ordering.
16.3.1 Capability Registers
The capability registers specify the software limits, restrictions, and capabilities of the host/device
controller implementation. Most of these registers are defined by the EHCI specification. Registers that
are not defined by the EHCI specification are noted in their descriptions.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-3. USB Interface Memory Map (continued)
Register
NOTE
Universal Serial Bus Interface
Access Reset
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
Mixed 0x0000_0000
— —
Section/Page
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16-7