Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 479

Offset 0x0_50C4
0
R
W
Reset
Bits Name
0–11 — Reserved
12–15 SBCE Single bit correctable error
There are at most four 512-byte page blocks (for a large page device) checked by ECC. A bit is set for
the 512-byte block that had a single bit correctable ECC error on read (bit 12 represents block 0, the first
512 bytes of a page; if ORx[PGS] = 0, bits 13–15 are always 0).
16–27 — Reserved
28–31 MBUE Multi bit uncorrectable error
There are at most four 512-byte page blocks (for a large page device) checked by ECC. A bit is set for
the 512-byte block that had an uncorrectable ECC error on read (bit 28 represents block 0, the first 512
bytes of a page; if ORx[PGS] = 0, bits 29–31 are always 0).
10.3.1.15 Local Bus Configuration Register (LBCR)
The local bus configuration register (LBCR) is shown in
Offset 0x0_50D0
0 1
R
LDIS
W
Reset 0 0 0
16
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
11 12
—
Figure 10-18. Transfer Error ECC Register (LTECCR)
Table 10-21. LTECCR Field Descriptions
—
0 0 0 0
BMT
Figure 10-19. Local Bus Configuration Register
15 16
SBCE
All zeros
Description
Figure 10-19.
7 8 9 10
BCTLC AHD
0 0 0 0
23 24
—
All zeros
Enhanced Local Bus Controller
Access: w1c
27 28
—
Access: Read/Write
11
—
0 0 1 0
27 28
BMTPS
31
MBUE
15
0
31
10-31