Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 905

The eTSEC clears the R bit in the first word of the BD after it finishes using the data buffer. The transfer
status bits are then updated. Additional transmit frame status can be found in statistic counters in the MIB
block.
Software must expect eTSEC to prefetch multiple TxBDs, and for TCP/IP checksumming an entire frame
must be read from memory before a checksum can be computed. Accordingly, the R bit of the first TxBD
in a frame must not be set until at least one entire frame can be fetched from this TxBD onwards. If eTSEC
prefetches TxBDs and fails to reach a last TxBD (with bit L set), it halts further transmission from the
current TxBD ring and report an underrun error as IEVENT[XFUN]; this indicates that an incomplete
frame was fetched, but remained unprocessed. The relevant TBPTR register points to the next unread
TxBD following the error.
Figure 15-146 defines the TxBD.
0 1
Offset + 0 R PAD/CRC
Offset + 2
Offset + 4
Offset + 6
The TxBD definition is interpreted by eTSEC hardware as if TxBDs mapped to C data structures in the
manner illustrated by Figure 15-147.
typedef unsigned short uint_16; /* choose 16-bit native type */
typedef unsigned int uint_32; /* choose 32-bit native type */
typedef struct txbd_struct {
uint_16 flags;
uint_16 length;
uint_32 bufptr;
} txbd;
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
2 3 4 5 6
W I L TC PRE/DEF
TX DATA BUFFER POINTER
Figure 15-146. Transmit Buffer Descriptor
Figure 15-147. Mapping of TxBDs to a C Data Structure
Enhanced Three-Speed Ethernet Controllers
7 8 9
0 HFE/LC CF/RL
DATA LENGTH
10 11 12 13 14
RC TOE/UN
15
TR
15-187