Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 384

Integrated Programmable Interrupt Controller (IPIC)
8.5.17 System External Interrupt Force Register (SEFCR)
Each implemented bit in SEFCR, shown in
a bit is set, the interrupt controller generates the corresponding external interrupt (sets the corresponding
SEPNR bit). SEFCR can be read by the user at any time.
Offset 0x
58
0 1
R
1
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4
W
Reset
16
R
W
Reset
1
IRQ0
This bit is valid only if
Figure 8-21. System External Interrupt Force Register (SEFCR)
Table 8-27 defines the bit fields of SEFCR.
Bits Name
0–4 IRQ n Each bit corresponds to an external interrupt source. The user force an interrupt by setting the SEFCR bit.
Note: SEFCR bit positions are not affected by their relative priority.
5–31 — Write ignored, read = 0
8.5.18 System Error Force Register (SERFR)
Each bit in the system error force register (SERFR), shown in
source. When a bit is set, the interrupt controller generates the corresponding MCP interrupt (sets the
corresponding SERSR bit). The SERFR can be read by the user at any time.
Offset 0x5C
0
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
8-26
Figure
2 3 4 5
is configured as an external maskable interrupt (SEMSR[S
Table 8-27. SEFCR Field Descriptions
INT n (Implemented bits are listed in
Figure 8-22. System Error Status Register (SERFR)
8-21, corresponds to an external interrupt source. When
—
All zeros
—
All zeros
IRQ0
Description
Figure 8-22, corresponds to an external MCP
Table 8-21.)
All zeros
Access: Read/write
] = 0)
Access: Read/write
Freescale Semiconductor
15
31
31