Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 56

Table
Number
4-31 RCR Bit Settings................................................................................................................... 4-36
4-32 RCER Bit Settings ................................................................................................................ 4-37
4-33 Clock Configuration Registers Memory Map....................................................................... 4-37
4-34 System PLL Mode Register Bit Settings .............................................................................. 4-38
4-35 OCCR Bit Settings ................................................................................................................ 4-39
4-36 SCCR Bit Descriptions ......................................................................................................... 4-40
5-1 Local Access Windows Target Interface................................................................................. 5-1
5-2 Local Access Windows Example............................................................................................ 5-2
5-3 Format of Window Definitions ............................................................................................... 5-3
5-4 Local Access Register Memory Map...................................................................................... 5-4
5-5 IMMRBAR Bit Settings.......................................................................................................... 5-7
5-6 ALTCBAR Bit Settings........................................................................................................... 5-7
5-7 LBLAWBAR0–LBLAWBAR3 Bit Settings........................................................................... 5-8
5-8 LBLAWBAR0[BASE_ADDR] Reset Value .......................................................................... 5-8
5-9 LBLAWAR0–LBLAWAR3 Bit Settings................................................................................. 5-9
5-10 LBLAWAR0[EN] Reset Value................................................................................................ 5-9
5-11 PCILAWBAR0–PCILAWBAR1 Bit Settings ...................................................................... 5-10
5-12 PCILAWBAR0[BASE_ADDR] Reset Value ....................................................................... 5-10
5-13 PCILAWAR0–PCILAWAR1 Bit Settings............................................................................. 5-11
5-14 PCILAWAR0[EN] Reset Value............................................................................................. 5-11
5-15 DDRLAWBAR0–DDRLAWBAR1 Bit Settings .................................................................. 5-12
5-16 DDRLAWBAR0[BASE_ADDR] Reset Value ..................................................................... 5-12
5-17 DDRLAWAR0–DDRLAWAR1 Bit Settings ........................................................................ 5-13
5-18 DDRLAWAR0[EN] Reset Value .......................................................................................... 5-14
5-19 Overlapping Local Access Windows .................................................................................... 5-14
5-20 System Configuration Register Memory Map ...................................................................... 5-16
5-21 SGPRL Bit Settings .............................................................................................................. 5-17
5-22 SGPRH Bit Settings .............................................................................................................. 5-17
5-23 SPRIDR Bit Settings ............................................................................................................. 5-18
5-24 PARTID Coding ................................................................................................................... 5-18
5-25 REVID Coding ..................................................................................................................... 5-18
5-26 SPCR Bit Settings ................................................................................................................. 5-19
5-27 SICRL Bit Settings................................................................................................................ 5-21
5-28 SICRH Bit Settings ............................................................................................................... 5-24
5-29 SICRH[30–31] Bit Settings .................................................................................................. 5-26
5-30 DDRCDR Field Descriptions................................................................................................ 5-27
5-31 DDRDSR Field Descriptions ................................................................................................ 5-28
5-32 WDT Register Address Map................................................................................................. 5-30
5-33 SWCRR Bit Settings ............................................................................................................. 5-31
5-34 SWCNR Bit Settings............................................................................................................. 5-32
5-35 SWSRR Bit Settings ............................................................................................................. 5-33
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Freescale Semiconductor