Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 264

System Configuration
Bits Name
4 GM2 Gate mode for TGATE2
0 Restart gate mode. The TGATE2 pin is used to enable/disable count. A low level of TGATE2 enables and
a falling edge of TGATE2 restarts the count (reset the dynamic counter's count value to 0) and a high
level of TGATE2 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not restart the
appropriate count value in GTCNR2[CNV2].
5 GM1 Gate mode for TGATE1
0 Restart gate mode. The TGATE1 is used to enable/disable count. A low level of TGATE1 enables and a
falling edge of TGATE1 restarts the count (reset the dynamic counter's count value to 0) and a high level
of TGATE1 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not restart the
appropriate count value in GTCNR1[CNV1].
Note: In backward compatible mode (GTCFR1[BCM] = 0) this bit is ignored. GTCFR1[GM2] bit will control
6 STP1 Stop timer 1
0 Normal operation
1 Reduce power consumption of the corresponding timer. This bit stops all clocks to the timer 1, except the
register interface clock, which allows to read and write timer registers. The clocks to the timer remain
stopped until the user clears this bit or a hardware reset occurs.
7 RST1 Reset timer 1
0 Reset the timer 1, including GTMDR1, GTRFR1, GTCNR1, GTCPR1, and GTEVR1 (a software reset is
identical to an external reset).
1 Enable the corresponding timer if the STP1 bit is cleared.
The GTCFR2 register is shown in
Offset 0x04
0
R
PCAS
W
Reset
Figure 5-41. Global Timers Configuration Register 2 (GTCFR2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-56
Table 5-57. GTCFR1 Bit Settings (continued)
the gate mode for timers 1 and 2.
Figure 5-41.
1 2
SCAS STP4
Description
3 4
RST4 GM4
All zeros
Access: Read/Write
5 6
GM3 STP3
Freescale Semiconductor
7
RST3