Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 316

Arbiter and Bus Monitor
4. Issues reset request, MCP or regular interrupt according to AERR[ATO] and AIDR[ATO], if
enabled by AMR[ATO].
5. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.2 Data Time Out
Data time out occurs, if the data tenure was not ended before the specified time-out period (programmed
by ATR[DTO]). In this case, the arbiter performs as follows:
1. Ends the data tenure by asserting transfer error.
2. Reports on this event in AER[DTO].
3. Issues reset request, MCP or regular interrupt according to AERR[DTO] and AIDR[DTO], if
enabled by AMR[DTO].
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.3 Transfer Error
The arbiter tracks the transfer error asserted by one of the slaves. In this case, the arbiter performs as
follows:
1. Reports on the event to AER[ETEA].
2. Issues reset request, MCP or regular interrupt according to AERR[ETEA] and AIDR[ETEA] if
enabled by AMR[ETEA].
3. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.4 Address Only Transaction Type
Table 6-10 shows transaction types, which are defined as address only:
The arbiter allows address-only (AO) transactions on the bus and the G2 core has ability to issue
address-only (AO) transactions (see HID0 [ABE] in the G2 PowerPC Core Reference Manual, Rev 1). As
there is no advantage in using AO transaction in this system, the bus monitor allows the detection of AO
transactions and treats them as an error.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
6-14
Table 6-10. Address Only Transaction Type Encoding
ttype[0:4]
00000
00100
01000
01100
10000
11000
00001
01001
01101
Bus Commands
Clean block
Flush block
Sync
Kill block
eieio
TLB Invalidate
lwarx reservation set
tlbsync
icbi
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