Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 168

Reset, Clocking, and Initialization
Signal I/O
SRESET I The SRESET input is connected directly to the soft reset input of the e300c3 core. The assertion of
the e300 soft reset input, SRESET, causes a high priority interrupt to the e300 core as described in
Section 4.2.1, "Reset Operations."
MPC8313E. The SRESET input is not registered in the reset status register (RSR).
State Meaning Asserted—Indicates that the processor must initiate a system reset interrupt.
Requirements An open-drain signal. An external pull-up is required.
CFG_RESET_ I Reset configuration word source selection. These signals are on device pins that have other functions
SOURCE[0:3] when the device is not in reset. They are sampled during the assertion of PORESET to determine the
interface from which the device loads the reset configuration words.
State Meaning See
Requirements During PORESET and HRESET flows, all other signal drivers connected to these
CFG_CLKIN_DIV I Clock in division selection. This signal is located on a device pin that has another function when the
device is not in reset state. This signal is sampled during the assertion of PORESET to determine
whether SYS_CLK_IN is divided by two.
State Meaning See
Requirements During PORESET and HRESET flows, all other signal drivers connected to this
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-2
Table 4-1. System Control Signals (continued)
Negated—Indicates that the interrupt is not being requested.
Timing Assertion—Occurs at any time, asynchronously to any clock.
Negation—Occurs after being serviced. (PCI host mode) or PCI_CLK (PCI agent
mode)
Reset State Always input
Section 4.3.1.1, "Reset Configuration Word
Timing These signals are sampled during the assertion of PORESET after a stable clock is
supplied (PORESET flow) and must be pulled high or low by external resistors as
long as HRESET is asserted.
signals must be in the high-impedance state. Refer to the hardware specifications
for proper resistor values to pull reset configuration signals high or low.
Reset State Input during power-on and hard reset flows. Functional signal after reset flow
completes.
Section 4.3.1.2, "SYS_CLK_IN Division."
Timing This signal is sampled during the assertion of PORESET after a stable clock is
supplied (PORESET flow), and it must be pulled high or low by external resistors as
long as HRESET is asserted.
signal must be in the high-impedance state. Refer to the hardware specifications for
proper resistors values to pull reset configuration signals high or low.
Reset State Always input
Description
It does not reset the e300 core or any other portion of the
Source."
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