Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 258

System Configuration
(GTRFR), a timer event register (GTEVR), and a timer global configuration register (GTCFR). The
GTPSRs and the GTMDRs contain the primary and secondary prescalers, programmed by the user.
Figure 5-39 shows the functional GTM block diagram.
GTCFR1
Global Configuration Register 1
GTCFR2
GTEVR1
GTPSR1
GTMDR1
GTCNR1
GTRFR1
GTCPR1
5.7.2 GTM Features
The key features of the timer include the following:
• The maximum input clock is the system bus clock
• Four 16-bit programmable timers
• Two timers cascaded internally or externally to form a 32-bit timer
• One timer cascaded internally or externally to form a 64-bit timer
• Maximum period of ~412.3 seconds (at 167-MHz bus clock and prescaler = 256) for 16-bit timer
• Maximum period of ~12.8825 seconds (at 167-MHz bus clock and prescaler = 256) for 32-bit timer
• Maximum period of thousands of years (at 167-MHz bus clock and prescaler = 256) for 64-bit
timer
• 3-nanosecond timer resolution (at 167-MHz bus clock and no prescaler)
• Resolution and maximum period can be traded off by selecting prescaler divisor
• Three programmable input clock sources for the timer prescalers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-50
Event Register
Prescale Register
Mode Register
Divider
16-Bit Counter
Reference Register
Capture Register
Registers Interface
Figure 5-39. Global Timers Block Diagram
General
System Clock
Timer
Clock
Generator
clock
Capture
Detection
Timer1
Timer2
Timer3
TGATE1
TGATE2
TGATE3
TGATE4
TIN1
TIN2
TIN3
TIN4
TOUT4
TOUT3
TOUT2
TOUT1
Timer4
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