Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 505

Table 10-34. Boot Bank Field Values after Reset for GPCM as Boot Controller (continued)
10.4.3 Flash Control Machine (FCM)
The FCM provides a glueless interface to parallel-bus NAND Flash EEPROM devices. The FCM contains
three basic configuration register groups—BR
Figure 10-44 shows a simple connection between an 8-bit port size NAND Flash EEPROM and the eLBC
in FCM mode. Commands, address bytes, and data are all transferred on LAD[0:7]
for transfers written to the device, or LFRE asserted for transfers read from the device. eLBC signals
LFCLE and LFALE determine whether writes are of type command (only LFCLE asserted), address (only
LFALE asserted), or write data (neither LFCLE nor LFALE asserted). The NAND Flash RDY/BSY pin is
normally open-drain, and should be pulled high by a 4.7-KΩ resistor. On system reset, a global (boot)
chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully
configured.
1. Note bit numbering reversal: LAD[0] (msb) connects to Flash IO[7], while LAD[7] (lsb) connects to IO[0].
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Register Field
OR0 AM
BCTLD
CSNT
ACS
XACS
SCY
SETA
TRLX
EHTR
EAD
, OR
n
Setting
0000_0000_0000_0000_0
0
1
11
1
1111
0
1
1
1
, and FMR.
n
Enhanced Local Bus Controller
1
, with LFWE asserted
10-57