Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 833

15.5.3.10.4 Timer PTP Packet Event Register (TMR_PEVENT)
The eTSEC precision timer logic can generate interrupts upon the capture of a timestamp due to either
transmission or reception of a frame. If an event occurs and its corresponding enable bit is set in the event
mask register (PEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event
register is cleared by writing a 1 to that bit position. Figure 15-107 describes the definition for the
TMR_PEVENT register.
Offset eTSEC1:0x2_4E0C
0
R
W
Reset
16
R
W
Reset
Table 15-113 describes the fields of the TMR_PEVENT register fields for the timer.
Bits Name
0–21 — Reserved
22 TXP2 Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS2 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
23 TXP1 Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS1 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
24–30 — Reserved
31 RXP Indicates that a PTP frame has been received
0 PTP packet not received
1 PTP packet has been received
15.5.3.10.5 Timer Event Mask Register (TMR_PEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_PEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset.
the definition for the TMR_PEMASK register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
21
—
Figure 15-107. TMR_PEVENT Register Definition
Table 15-113. TMR_PEVENT Register Field Descriptions
Enhanced Three-Speed Ethernet Controllers
—
All zeros
22 23 24
TXP2 TXP1
All zeros
Description
Access: Read/Write
15
30 31
— RXP
Figure 15-108 describes
15-115