Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 990

Universal Serial Bus Interface
16.5.6 Queue Head
Figure 16-41 shows the queue head structure.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL C Maximum Packet Length
Mult Port Number
1
dt Total Bytes to Transfer
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
1
Offsets 0x04 through 0x0B contain the static endpoint state.
2
Host controller read/write; all others read-only.
3
Offsets 0x10 through 0x2F contain the transfer overlay.
4
Offsets 0x14 through 0x27 contain the transfer results.
16.5.6.1 Queue Head Horizontal Link Pointer
The first DWord of a queue head contains a link pointer to the next data object to be processed after any
required processing in this queue has been completed, as well as the control bits defined below.
This pointer may reference a queue head or one of the isochronous transfer descriptors. It must not
reference a queue element transfer descriptor.
Bits Name
31–5 QHLP Queue head horizontal link pointer. This field contains the address of the next data object to be processed in
the horizontal list and corresponds to memory address signals [31:5], respectively.
4–3 — Reserved, should be cleared. These bits must be written as zeros.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-62
15
Queue Head Horizontal Link Pointer
H
Hub Addr
Current qTD Pointer
2
Next qTD Pointer
Alternate Next qTD Pointer
2 2
ioc
2
2
2
2
2
Figure 16-41. Queue Head Layout
Table 16-57. Queue Head DWord 0
14 13 12 11 10 9 8
dtc EPS EndPt
µFrame C-mask
2
2
PID
2 2
C_Page Cerr
2
Code
0000
S-bytes
Description
7 6 5 4 3 2 1
00 Typ
I Device Address
µFrame S-mask
00000
0000
2
NakCnt
2
Status
2
Current Offset
2
C-prog-mask
2
FrameTag
0000_0000_0000
0000_0000_0000
Freescale Semiconductor
0 offset
T 0x00
1
0x04
1
0x08
0x0C
2 3
T 0x10
2 3,4
T 0x14
3,4
0x18
3,4
0x1C
3,4
0x20
2 3,4
0x24
3
0x28
3
0x2C