Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 206

Reset, Clocking, and Initialization
4.5.2.3 System Clock Control Register (SCCR)
SCCR, shown in Figure
Address 0x0_0A08
0 1
R
TSEC
TSECCM
1ON
W
Reset 0 1
16
R
W
Reset 1 1
Table 4-36 defines the bit fields of SCCR.
Bits Name
0–1 TSECCM TSEC1 and TSEC2 clock mode.
00 Reserved. Write not allowed. If written, treated as ratio 1:1.
01 TSEC1&2 clock/ csb_clk ratio is 1:1.
10 TSEC1&2 clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than TSEC1&2).
11 TSEC1&2 clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than TSEC1&2).
2 TSEC1ON TSEC1 clock switch off
0 TSEC1 clock is disabled.
1 TSEC1 clock is enabled and in the ratio as specified by TSECCM.
3 TSEC2ON TSEC2 clock switch off
0 TSEC2 clock is disabled.
1 TSEC2 clock is enabled and in the ratio as specified by TSECCM.
4–5 — Reserved
6–7 ENCCM Encryption core and I
00 Encryption core clock is disabled.
01 Encryption core clock/ csb_clk ratio is 1:1.
10 Encryption core clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than the encryption core).
11 Encryption core clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than the encryption core).
8–9 — Reserved
10–11 USB USB DR clock mode.
DRCM 00 USB DR clock is disabled.
01 USB DR clock/ csb_clk ratio is 1:1.
10 USB DR clock/ csb_clk ratio is 1:2 ( csb_clk has higher frequency than the USB DR).
Note: 11USB DR clock/ csb_clk ratio is 1:3 ( csb_clk has higher frequency than the USB DR).
12–14 — Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-40
4-15, controls device units that have a configurable clock ratio.
2 3 4 5
TSEC2
—
ON
1 1 1 1
1 1 1 1
Figure 4-15. System Clock Control Register (SCCR)
Table 4-36. SCCR Bit Descriptions
2
C1 clock mode.
6 7 8 9
ENCCM — USBDRCM
0 1 1 1
—
1 1 1 1
Description
Access: Read/Write
10 11 12
—
0 1 1 1
1 1 1 1
Freescale Semiconductor
14 15
PCICM
1 1
31
1 1