Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 626

PCI Bus Interface
The PCI internal arbiter supports three external masters (besides the PCI controller itself) by using the
REQ signals and generating the GNT signals.
During reset, the PCI controller samples the reset configuration bit (and programs the PCI_ARB_DIS bit
accordingly) to determine if the arbiter is enabled or disabled.
Initialization," for more information. The arbiter can also be enabled or disabled by directly programming
the PCI_ARB_DIS bit in the arbiter configuration register (see
Register (PCIACR)," for more information). However, it is recommended to use the reset configuration
bit to set the arbiter state because the arbiter state controls the direction of REQ0 and GNT0.
If the arbiter is disabled, the PCI controller uses REQ0 to issue requests to an external arbiter, and uses
GNT0 to receive grants from the external arbiter.
13.4.1.1 Bus Parking
When no devices are requesting the bus, the bus is granted, or parked, for a specified device to prevent the
AD, PCI_C/BE and PCI_PAR signals from floating. The PCI controller can be configured to either park
on itself or park on the last master to use the bus (see
(PCIACR)," for more information).
13.4.1.2 Arbitration Algorithm
The round-robin arbitration algorithm has two priority levels. Each of the external PCI bus masters, plus
the PCI controller, are assigned either a high or a low priority level, as programmed in the arbiter
configuration register (see
priority group (high or low), the bus grant is given to the next requesting device in numerical order, with
the PCI controller itself positioned before device 0. GNTn is asserted for device n as soon as the previously
granted device begins a transaction. Conceptually, the lowest priority device at any given time is the
current bus master and the highest priority device is the next one to follow the current master. This is
considered to be a fair algorithm because a given device cannot prevent other devices from having access
to the bus—a given device automatically becomes the lowest priority device as soon as it begins to use the
bus. If a master is not requesting the bus, the transaction slot is given to the next requesting device within
the priority group.
The grant given to one device may be taken away and whenever a higher priority device asserts its request.
If the bus is idle when a new device is to receive a grant, no device receives a grant for one clock; in the
next clock, the new winner of the arbitration receives a grant. This operation allows for a turnaround clock
when a device is using address stepping or when the bus is parked.
The low priority group collectively receives one bus transaction request slot in the high priority group.
Therefore, if there are N high-priority devices, each high-priority device is guaranteed to get at least one
of (N+1) bus transactions, and the M low priority devices are guaranteed to each get at least one of (N+1)
x M bus transactions, with one of the low-priority devices receiving the grant in one of (N+1) bus
transactions. If all devices are programmed to the same priority level or if there is only one device at the
low priority, the algorithm provides each device an equal number of bus grants in a round-robin sequence.
An arbitration example with three masters in the high priority group and two in the low priority group is
shown in Figure 13-47. Noting that one position in the high priority group is actually a place-holder for
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-44
Section 13.3.3.25, "PCI Arbiter Control Register
SeeChapter 4, "Reset, Clocking, and
Section 13.3.3.25, "PCI Arbiter Control
Section 13.3.3.25, "PCI Arbiter Control Register
(PCIACR).") Within each
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