Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 20

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Number
13.3.3.28 PCI Power Management Register 1 (PCIPMR1) ................................................ 13-42
13.4 Functional Description................................................................................................. 13-43
13.4.1 PCI Bus Arbitration ................................................................................................. 13-43
13.4.1.1 Bus Parking.......................................................................................................... 13-44
13.4.1.2 Arbitration Algorithm.......................................................................................... 13-44
13.4.1.3 Broken Master Lock-Out ..................................................................................... 13-45
13.4.1.4 Master Latency Timer.......................................................................................... 13-45
13.4.2 Bus Commands ........................................................................................................ 13-46
13.4.3 PCI Protocol Fundamentals ..................................................................................... 13-47
13.4.3.1 Basic Transfer Control......................................................................................... 13-47
13.4.3.2 Addressing ........................................................................................................... 13-47
13.4.3.3 Device Selection .................................................................................................. 13-48
13.4.3.4 Byte Enable Signals............................................................................................. 13-48
13.4.3.5 Bus Driving and Turnaround ............................................................................... 13-48
13.4.3.6 Bus Transactions.................................................................................................. 13-49
13.4.3.7 Read and Write Transactions ............................................................................... 13-49
13.4.3.8 Transaction Termination ...................................................................................... 13-51
13.4.4 Other Bus Operations............................................................................................... 13-53
13.4.4.1 Fast Back-to-Back Transactions .......................................................................... 13-53
13.4.4.2 Dual Address Cycles............................................................................................ 13-54
13.4.4.3 Data Streaming .................................................................................................... 13-54
13.4.4.4 Host Mode Configuration Access........................................................................ 13-54
13.4.4.5 Agent Mode Configuration Access ..................................................................... 13-55
13.4.4.6 Special Cycle Command...................................................................................... 13-55
13.4.4.7 Interrupt Acknowledge ........................................................................................ 13-56
13.4.5 Error Functions ........................................................................................................ 13-57
13.4.5.1 Parity.................................................................................................................... 13-57
13.4.5.2 Error Reporting.................................................................................................... 13-57
13.4.6 PCI Inbound Address Translation............................................................................ 13-59
13.4.7 CompactPCI Hot Swap Specification Support ........................................................ 13-60
13.5 Initialization/Application Information ......................................................................... 13-60
13.5.1 Initialization Sequence for Host Mode .................................................................... 13-60
13.5.2 Initialization Sequence for Agent Mode.................................................................. 13-60
14.1 SEC 2.2 Architecture Overview .................................................................................... 14-2
14.1.1 Descriptors ................................................................................................................. 14-3
14.1.2 Execution Units (EUs) ............................................................................................... 14-5
14.1.2.1 Data Encryption Standard Execution Unit (DEU)................................................. 14-5
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Contents
Title
Chapter 14
Security Engine (SEC) 2.2
Page
Number
Freescale Semiconductor