Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 802

Enhanced Three-Speed Ethernet Controllers
Table 15-64 describes the fields of the RPKT register.
Bits Name
0–9 — Reserved
10-31 RPKT Receive packet counter. Increments for each frame received packet (including bad packets, all unicast,
broadcast, and multicast packets).
15.5.3.6.10 Receive FCS Error Counter (RFCS)
Figure 15-61 describes the definition for the RFCS register.
Offset eTSEC1:0x2_46A4; eTSEC2:0x2_56A4
0
R
W
Reset
Table 15-65 describes the fields of the RFCS register.
Bits Name
0–15 — Reserved
16–31 RFCS Receive FCS error counter. In Ethernet mode, increments for each frame received that has an integral
64–1518 length and contains a frame check sequence error.
15.5.3.6.11 Receive Multicast Packet Counter (RMCA)
Figure 15-62 describes the definition for the RMCA register.
Offset eTSEC1:0x2_46A8; eTSEC2:0x2_56A8
0
R
W
Reset
Figure 15-62. Receive Multicast Packet Counter Register Definition
Table 15-66 describes the fields of the RMCA register.
Bits Name
0–9 — Reserved
10–31 RMCA Receive multicast packet counter. Increments for each multicast frame with valid CRC and of lengths 64 to
1518 (non VLAN) or 1522 (VLAN), excluding broadcast frames. This count does not include range/length
errors.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Table 15-64. RPKT Field Descriptions
—
Figure 15-61. Receive FCS Error Counter Register Definition
Table 15-65. RFCS Field Descriptions
9 10
—
Table 15-66. RMCA Field Descriptions
Description
15 16
All zeros
Description
RMCA
All zeros
Description
Access: Read/Write
RFCS
Access: Read/Write
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