Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 901

Figure 15-142 depicts the buffer format requirements for timestamp insertion on transmit packets.
TX BD Ring
Data Buffer Length=8
Data Buffer Pointer
Data Buffer Length=M
Data Buffer Pointer
Figure 15-142. Buffer Format for Transmit timestamp Insertion
15.6.6.5.2 Error Condition
When an error is encountered after a PTP packet has begun to be processed, the timestamp written to the
TxPAL is zero. Subsequent frames may be flushed by eTSEC. There will be no timestamp update to
TxPAL for the subsequent flushed frames.
15.6.6.6 Tx PTP Packet Parsing
Software instructs the Tx packet to be timestamped via setting bit 15 in the TxFCB to mark a PTP packet.
TxFCB[VLCTL] can be translated as the Tx PTP packet identification number. BD[TOE] must be set to
enable transmit PTP packet timestamping. TxFCB[PTP] bit takes precedence over TxFCB[VLN] bit. It
disables per packet VLAN tag insertion. On a PTP packet, a VLAN tag can be inserted from the DFVLAN
register. The TxFCB for the PTP packet is shown in
0
Offset + 0 VLN
Offset + 2
Offset + 4
Offset + 6
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
TOE=1
1 2 3 4 5
IP IP6 TUP UDP CIP CTU NPH
L4OS
Figure 15-143. Transmit Frame Control Block
Enhanced Three-Speed Ethernet Controllers
External Memory
32B cache-lines
0 1 2
FCB
8 Bytes
Figure 15-143.
6 7 8 9 10
PHCS
VLCTL/PTP_ID
3 ... 7
TxFCB
TxPAL
TxPAL
TxPAL
Unknown
Unknown
FRAME
11 12 13 14
PTP
L3OS
15
15-183