Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 733

eTSEC1
Offset
0x2_4334 RQFAR*—Receive queue filing table address register
0x2_4338 RQFCR*—Receive queue filing table control register
0x2_433C RQFPR*—Receive queue filing table property register
0x2_4340 MRBLR—Maximum receive buffer length register
0x2_4344– Reserved
0x2_4380
0x2_4380 RBDBPH*—Rx data buffer pointer high bits
0x2_4384 RBPTR0—RxBD pointer for ring 0
0x2_4388 Reserved
0x2_438C RBPTR1*—RxBD pointer for ring 1
0x2_4390 Reserved
0x2_4394 RBPTR2*—RxBD pointer for ring 2
0x2_4398 Reserved
0x2_439C RBPTR3*—RxBD pointer for ring 3
0x2_43A0 Reserved
0x2_43A4 RBPTR4*—RxBD pointer for ring 4
0x2_43A8 Reserved
0x2_43AC RBPTR5*—RxBD pointer for ring 5
0x2_43B0 Reserved
0x2_43B4 RBPTR6*—RxBD pointer for ring 6
0x2_43B8 Reserved
0x2_43BC RBPTR7*—RxBD pointer for ring 7
0x2_43C0– Reserved
0x2_44400
0x2_4404 RBASE0—RxBD base address of ring 0
0x2_4408 Reserved
0x2_440C RBASE1*—RxBD base address of ring 1
0x2_4410 Reserved
0x2_4414 RBASE2*—RxBD base address of ring 2
0x2_4418 Reserved
0x2_441C RBASE3*—RxBD base address of ring 3
0x2_4420 Reserved
0x2_4424 RBASE4*—RxBD base address of ring 4
0x2_4428 Reserved
0x2_442C RBASE5*—RxBD base address of ring 5
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 15-4. Module Memory Map (continued)
1
Name
Enhanced Three-Speed Ethernet Controllers
2
Access Reset
R/W 0x0000_0000
0x nnnn_nnnn
R/W
R/W 0x nnnn_nnnn
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
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