Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 614

PCI Bus Interface
13.3.3.9 Cache Line Size Configuration Register
Figure 13-27 shows the cache line size fields.
Offset 0C
7
R
W
Reset
Table 13-31 shows the bit settings of the cache line size register.
Table 13-31. Cache Line Size Configuration Register Field Descriptions
Bits Name
7–0 CLS
13.3.3.10 Latency Timer Configuration Register
Figure 13-28 shows the latency timer fields.
Offset 0D
7
R
W
Reset
Table 13-32 shows the bit settings of the latency timer register.
Table 13-32. Latency Timer Configuration Register Field Descriptions
Bits Name
7–3 LT
2–0 —
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
13-32
Figure 13-27. Cache Line Size Configuration Register
Cache line size. Cache-line in terms of 32-bit words. Although the register is writable, only the value
0x08 is legal.
LT
Figure 13-28. Latency Timer Configuration Register
Latency timer. Specifies a granularity of 8 PCI clocks, the length of time that the PCI controller, when
mastering a transaction, may hold the bus as the result of a bus grant. Refer to the PCI 2.3
specification for the rules by which the PCI controller completes transactions when the timer has
expired.
Reserved
CLS
All zeros
Description
3 2
All zeros
Description
Access: Read/Write
0
Access: Read/Write
0
—
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