Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 999

Port Status and Signaling Type
Port disabled, resume K-State received
Port suspended, Resume K-State
received
Port is enabled, disabled or suspended,
and the port's WKDSCNNT_E bit,
PORTSC[WKDS], is set. A disconnect is
detected.
Port is enabled, disabled or suspended,
and the port's WKDSCNNT_E bit,
PORTSC[WKDS], is cleared. A
disconnect is detected.
Port is not connected and the port's
WKCNNT_E bit is a one. A connect is
detected.
Port is not connected and the port's
WKCNNT_E bit is a zero. A connect is
detected.
Port is connected and the port's
WKOC_E bit is a one. An over-current
condition occurs.
Port is connected and the port's
WKOC_E bit is a zero. An over-current
condition occurs.
1
Hardware interrupt issued if USBINTR[PCE] (port change interrupt enable) is set.
2
PME# asserted if enabled (Note: PME Status must always be set).
3
PME# not asserted.
16.6.5 Schedule Traversal Rules
The host controller executes transactions for devices using a simple, shared-memory schedule. The
schedule is comprised of a few data structures, organized into two distinct lists. The data structures are
designed to provide the maximum flexibility required by USB, minimize memory traffic and
hardware/software complexity.
System software maintains two schedules for the host controller: a periodic schedule and an asynchronous
schedule. The root of the periodic schedule is the PERIODICLISTBASE register. See
"Periodic Frame List Base Address Register (PERIODICLISTBASE),"
PERIODICLISTBASE register is the physical memory base address of the periodic frame list. The
periodic frame list is an array of physical memory pointers. The objects referenced from the frame list must
be valid schedule data structures as defined in
if the periodic schedule is enabled (see) then the host controller must execute from the periodic schedule
before executing from the asynchronous schedule. It will only execute from the asynchronous schedule
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 16-64. Behavior During Wake-Up Events
Signaled Port Response
No effect
Resume reflected downstream on signaled port.
PORTSC[FPR] is set. USBSTS[PCI] is set.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
Depending on the initial port state, the PORTSC Connect
(CCS) and Enable (PE) status bits are cleared, and the
Connect Change status bit (CSC) is set. USBSTS[PCI] is set.
PORTSC Connect Status (CCS) and Connect Status Change
(CSC) bits are set. USBSTS[PCI] is set.
PORTSC Connect Status (CCS) and Connect Status Change
(CSC) bits are set. USBSTS[PCI] is set.
PORTSC Over-current Active (OCA), Over-current Change
(OCC) bits are set. If Port Enable/Disable bit (PE) is a one, it is
cleared. USBSTS[PCI] is set
PORTSC Over-current Active (OCA), Over-current Change
(OCC) bits are set. If Port Enable/Disable bit (PE) is a one, it is
cleared. USBSTS[PCI] is set.
Section 16.5, "Host Data Structures."
Universal Serial Bus Interface
Device State
D0
N/A
[1], [2]
[1], [2]
[1], [3]
[1], [2]
[1], [3]
[1], [2]
[1], [3]
Section 16.3.2.6,
for more information. The
In each micro-frame,
not D0
N/A
[2]
[2]
[3]
[2]
[3]
[2]
[3]
16-71