Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 276

System Configuration
5.8.2.2 Power Management Controller Event Register (PMCER)
The power management controller event register (PMCER), shown in
PMCI bit that the power management controller has detected a wake-up event, that the system is not in
idle state anymore, and that the device should exit low power state. If PMCMR[PMCIE] is set, the PMC
interrupt request to the PowerPC core is driven. When set, bits 23–30 indicate the sources of various
wake-up events.
Offset 0x00B04
0
R
W
Reset
16
R
—
W
Reset
Table 5-68 defines the bit fields of PMCER.
Bits Name
0–22 — Reserved. Write has no effect, read returns 0.
23 GPIO Wake-up event detected.
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred on GPIO. This wake-up event was caused by an unmasked event of GPIO
module. See
bit is set, the PMC will assert interrupt request to the PowerPC core or external PME to the remote host,
depending on the state of PMCCR1[PME_EN]. This bit can be cleared by writing a 1 to the bit location
(writing zero has no effect).
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
24 PCI Wake-up event detected.
(PME) 0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred. This wake up event was caused by an active state of the PCI_PME input
signal. See
corresponding PMCMR bit is set, the PMC will assert interrupt request to the PowerPC core. This bit can
be cleared by writing a 1 to the bit location (writing zero has no effect).
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
25 USB Wake-up event detected.
0 A wake-up event did not occur from this wake-up source.
1 A wake-up event occurred on USB. This wake-up event was caused by a detection of a non idle state on
USB interface. See
PMCMR bit is set, the PMC will assert interrupt request to the PowerPC core or external PME to the
remote host, depending on the state of PMCCR1[PME_EN]. This bit can be cleared by writing a 1 to the
bit location (writing zero has no effect).
Note: This bit will not be affected by the wake-up event if the corresponding mask bit in PMCMR is cleared.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-68
22 23
GPIO PCI (PME)
Figure 5-52. Power Management Controller Event Register
Table 5-68. PMCER Bit Settings
Chapter 21, "General Purpose I/O (GPIO),"
Table 13-3, "PCI Interface Signals—Detailed Signal Descriptions,"
Chapter 16, "Universal Serial Bus Interface,"
—
All zeros
24 25 26
USB eTSEC1 eTSEC2 Timer
All zeros
Description
for more details. If the corresponding PMCMR
Figure 5-52, indicates with the
Access: Read/Write
27 28 29
Int1
for more details. If the
for more details. If the corresponding
Freescale Semiconductor
15
30 31
Int2 PMCI