Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 89

System
Register
Unit
+
Integer
Units (2)
/ +
*
XER
Completion
Unit
Power
Dissipation
Control
JTAG/COP
Interface
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Instruction
Dispatch Unit
32-Bit
GPR File
GP Rename
Registers
Time Base
Counter/
Decrementer
Clock
Multiplier
Touch Load Buffer
Copy-Back Buffer
32-Bit Address Bus
64-Bit Data Bus
Figure 1-2. MPC8313E Integrated e300c3 Core Block Diagram
64-Bit
Sequential
Fetcher
64-Bit
Queue
64-Bit
Instruction Unit
64-Bit
64-Bit
FPR File
Load/Store
Unit
FP Rename
Registers
+
32-Bit
D MMU
SRs
64-Bit
DBAT
Array
DTLB
16-Kbyte
Tags
D Cache
64-Bit
Branch
Processing
Unit
CTR
CR
LR
64-Bit
Floating-
Point Unit
+
/
*
FPSCR
I MMU
SRs
IBAT
Array
ITLB
16-Kbyte
Tags
I Cache
Processor Logic
Bus Interface
Overview
1-9