Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 86

Overview
— On-chip digital filtering rejects spikes on the bus
• I/O sequencer
• DMA (Direct memory access) controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible by local core and remote PCI masters
— Misaligned transfer capability for source/destination address
— Data chaining and direct mode
— Interrupt on completed segment and chain
• DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• Serial peripheral interface (SPI)
— Master or slave support
• Power management controller (PMC)
— Provides power management when the device is used in both host and agent modes
— Supports PCI Power Management 1.2 D0, D1, D2, D3hot, and D3cold states
— On-chip split power supply controlled through external power switch for minimum standby
power
— Supports PME generation in PCI agent mode and PME detection in PCI host mode
— Supports wake-up from Ethernet Magic Packet, USB, GPIO, PCI (PME input as host), timer
and external interrupts
— Supports MPC8349E backward-compatibility mode
• Parallel I/O
— General-purpose I/O (GPIO)
– 32 parallel I/O pins multiplexed on various chip interfaces
– One dedicated GPIOs
— Open drain capability
— Interrupt capability
• System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Two general-purpose timers
• IEEE Std. 1149.1™ compliant JTAG boundary scan
• Integrated PCI bus and SDRAM clock generation
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1-6 Freescale Semiconductor