Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 676

Security Engine (SEC) 2.2
14.4.2.6 MDEU Status Register (MDEUSR)
The MDEU status register (MDEUSR), as seen in
signals. The majority of these internal signals reflect the state of low-level MDEU functions, such as data
padding, key padding, and so on, and are not important to the user, however the user should be aware that
reads of this register especially during processing are likely to return non-zero values for many bits
between 0–57. The four signals shown are those which are most likely to be of interest to the user.
The MDEUSR is read-only. Writing to this location will result in address error being reflected in the
MDEUISR.
0
Field
Reset
R/W
Addr
Table 14-22 describes the MDEUSR fields.
Bits Name
0–57 — Reserved
58 HALT Halt. Indicates that the MDEU has halted due to an error.
0 MDEU not halted
1 MDEU halted
Note: Because the error causing the MDEU to stop operating may be masked before reaching the interrupt
status register, the MDEUISR is used to provide a second source of information regarding errors
preventing normal operation.
59–60 ICR Integrity check result
00 No integrity check was performed.
01 The integrity check passed.
10 The integrity check failed.
11 Reserved
61 IE Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 MDEU is not signaling error
1 MDEU is signaling error
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
14-34
Figure
—
MDEU 0x3_6028
Figure 14-20. MDEU Status Register (MDEUSR)
Table 14-22. MDEUSR Field Descriptions
(Section 14.6.4.3, "Interrupt Status Register
14-20, reflects the state of the MDEU internal
57 58 59
HALT
0
R
Description
(ISR)").
60 61 62 63
ICR IE ID RD
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