Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 184

Reset, Clocking, and Initialization
When the boot sequencer is enabled, the e300 core must be prevented from
fetching boot code, by setting the core disable reset configuration word field
(COREDIS) as described in
High Register (RCWHR)."
sequencer should enable boot vector fetch by clearing ACR[COREDIS] as
described in
4.3.2.2.4 Boot ROM Location
The device defines the default boot ROM address range to be 8 Mbytes at addresses 0x0000_0000 to
0x007F_FFFF or 0xFF80_0000 to 0xFFFF_FFFF (selected by the BMS reset configuration word field).
However, the on-chip peripheral that manages these boot ROM accesses can be selected at power up.
The boot ROM location reset configuration word field, shown in
boot ROM. The exact boot ROM location table to be used is defined by the setting of RCWHR[RLEXT]
bits, as shown in Table
address map are directed to the interface specified by this field.
RCWHR Field
Bits Name (Binary)
9–11 ROMLOC
The local access window of the selected boot ROM interface is enabled and initialized with the proper base
address and size, as described in
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-18
Section 4.3.2.2, "Reset Configuration Word
If the e300 core is required to proceed, the boot
Section 6.2.1, "Arbiter Configuration Register (ACR)."
4-11. Accesses to the boot vector and the default boot ROM region of the local
Table 4-15. Boot ROM Location
Value
Legacy Mode (RLEXT = 00)
000 DDR SDRAM
001 PCI
010 Reserved, should be cleared.
011 Reserved, should be cleared.
100 Reserved
101 Local bus GPCM—8-bit ROM
110 Local bus GPCM—16-bit ROM
111 Reserved
Section 5.2, "Local Memory Map Overview and Example."
NOTE
Table
Meaning
Reserved
Local bus NAND Flash—8-bit small page
ROM
Reserved
Reserved
Reserved
Local bus NAND Flash—8-bit large page
ROM
Reserved
Reserved
4-15, establishes the location of
NAND Flash Mode (RLEXT = 01)
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