Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 740

Enhanced Three-Speed Ethernet Controllers
eTSEC1
Offset
0x2_4EA0 TMR_ETTS1_H*—Timestamp of general purpose external
trigger
0x2_4EA4 TMR_ETTS1_L*—Timestamp of general purpose external trigger
0x2_4EA8 TMR_ETTS2_H*—Timestamp of general purpose external
trigger
0x2_4EAC TMR_ETTS2_L*—Timestamp of general purpose external trigger
0x2_4EB0 Reserved
–
0x2_4FFF
0x2_5000– eTSEC2 REGISTERS
0x2_5FFF
1
Registers denoted * are new to the enhanced TSEC and not supported by PowerQUICC II Pro TSECs.
2
Key: R = read only, WO = write only, R/W = read and write, LH = latches high, SC = self-clearing.
3
Cleared on read.
4
eTSEC2 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_5000 to 0x2_5FFF.
15.5.3 Memory-Mapped Register Descriptions
This section provides a detailed description of all the eTSEC registers. Because all of the eTSEC registers
are 32 bits wide, only 32-bit register accesses are supported.
15.5.3.1 eTSEC General Control and Status Registers
This section describes general control and status registers used for both transmitting and receiving Ethernet
frames. All of the registers are 32 bits wide.
15.5.3.1.1 Controller ID Register (TSEC_ID)
The controller ID register (TSEC_ID) is a read-only register. The TSEC_ID register is used to identify the
eTSEC block and revision.
Offset eTSEC1:0x2_4000; eTSEC2:0x2_5000
0
R
W
Reset 0 0 0 0 0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-22
Table 15-4. Module Memory Map (continued)
1
Name
4
TSEC_ID
0 0 1 0 0 1 0 0
Figure 15-2. TSEC_ID Register
Access
R/W
R/W
R/W
R/W
—
Other eTSECs
15 16
TSEC_REV_MJ
1 0 0 0 0 0 0
2
Reset Section/Page
0x0000_0000 15.5.3.10.14/15-121
0x0000_0000
0x0000_0000
0x0000_0000
—
Access: Read only
23 24
TSEC_REV_MN
0 0 0 1 0 0 0 0
Freescale Semiconductor
—
31
0 1 1 0