Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 17

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Number
10.5.4.4 NAND Flash Page Read Command Sequence Example ..................................... 10-95
10.5.4.5 NAND Flash Block Erase Command Sequence Example .................................. 10-96
10.5.4.6 NAND Flash Program Command Sequence Example ........................................ 10-96
10.5.5 Interfacing to Fast-Page Mode DRAM Using UPM ............................................... 10-97
10.5.6 Interfacing to ZBT SRAM Using UPM................................................................. 10-102
11.1 Overview........................................................................................................................ 11-1
11.1.1 Features...................................................................................................................... 11-2
11.2 External Signal Description ........................................................................................... 11-2
11.3 Memory Map/Register Definition ................................................................................. 11-2
11.4 Register Descriptions ..................................................................................................... 11-3
11.4.1 PCI Outbound Translation Address Registers (POTARn)......................................... 11-3
11.4.2 PCI Outbound Base Address Registers (POBARn) .................................................. 11-3
11.4.3 PCI Outbound Comparison Mask Registers (POCMRn) .......................................... 11-4
11.4.4 Power Management Control Register (PMCR) ......................................................... 11-5
11.4.5 Discard Timer Control Register (DTCR) .................................................................. 11-6
11.5 Functional Description................................................................................................... 11-6
11.5.1 Transaction Forwarding ............................................................................................. 11-6
11.5.1.1 Transactions from the Coherency System Bus (CSB) Port ................................... 11-7
11.5.1.2 Transactions from the PCI Port ............................................................................. 11-7
11.5.1.3 Transactions from the DMA Port .......................................................................... 11-7
11.5.2 PCI Outbound Address Translation ........................................................................... 11-7
11.5.3 Transaction Ordering ................................................................................................. 11-8
12.1 Features .......................................................................................................................... 12-1
12.2 Memory Map/Register Definition ................................................................................. 12-2
12.3 Register Descriptions ..................................................................................................... 12-3
12.3.1 Outbound Message Interrupt Status Register (OMISR) ............................................ 12-3
12.3.2 Outbound Message Interrupt Mask Register (OMIMR)............................................ 12-4
12.3.3 Inbound Message Registers (IMR0–IMR1) .............................................................. 12-5
12.3.4 Outbound Message Registers (OMR0–OMR1)......................................................... 12-5
12.3.5 Doorbell Registers ..................................................................................................... 12-6
12.3.5.1 Outbound Doorbell Register (ODR)...................................................................... 12-6
12.3.5.2 Inbound Doorbell Register (IDR).......................................................................... 12-7
12.3.6 Inbound Message Interrupt Status Register (IMISR) ................................................ 12-7
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Contents
Title
Chapter 11
Sequencer
Chapter 12
DMA/Messaging Unit
Page
Number
xvii