Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 575

Bits Name
2–1 — Reserved
0 EOTD End-of-transfer descriptor.
0 This descriptor contains a link to another descriptor.
1 This descriptor is the last to be executed.
12.3.8.8 DMA General Status Register (DMAGSR)
DMAGSR provides faster access to the status bits by combining the status bits of all of the DMA channels
into one register. Each byte of this register provides the value of bits 7–0 of a channel's DMA status
register. These bits are cleared by writing to the individual DMA status registers.
DMAGSR fields.
Offset 0x2A8
31
R
Channel 0 Status
W
Reset
12.4 Functional Description
12.4.1 Message Unit
An embedded processor is often part of a larger system containing many processors and distributed
memory. These processors tend to work on tasks independent of the host and other peripheral processors
in the system. Because of the independent nature of the tasks, it is necessary to provide a communication
mechanism between the peripheral processors and the rest of the system. One such method is the use of
messages. This block provides a messaging unit to further facilitate communications between host and
peripheral. The message unit uses generic messages and doorbell registers.
12.4.1.1 Messaging Registers (IMR0–IMR1, OMR0–OMR1)
There are two 32-bit inbound message registers (IMR0–IMR1) and two 32-bit outbound message registers
(OMR0–OMR1). IMR0 and IMR1 allow a remote host or PCI master to write a 32-bit value that, in turn,
causes an interrupt request to the on-chip interrupt controller that drives an interrupt line to the local
processor. OMR0 and OMR1 allow the local processor to write an outbound message which, in turn,
causes the outbound interrupt signal PCI_INTA to assert.
The interrupt to the local processor is cleared by writing 1 to the appropriate IMISR bit. The interrupt to
PCI (PCI_INTA) is cleared by writing 1 to the appropriate OMISR bit.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 12-16. DMANDAR n Field Descriptions (continued)
24 23
Channel 1 Status
Figure 12-17. DMA General Status Register (DMAGSR)
Descriptions
16 15
Channel 2 Status
All zeros
DMA/Messaging Unit
Figure 12-17 shows the
Access: User Read/Write
8 7
Channel 3 Status
12-15
0