Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 801

15.5.3.6.7 Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter (TRMGV)
Figure 15-58 describes the definition for the TRMGV register.
Offset eTSEC1:0x2_4698; eTSEC2:0x2_5698
0
R
—
W
Reset
Figure 15-58. Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition
Table 15-62 describes the fields of the TRMGV register.
Bits Name
0–9 — Reserved
10–31 TRMGV Increments for each good or bad frame transmitted and received which is 1519–1522 bytes in length,
inclusive (excluding preamble and SFD but including FCS bytes).
15.5.3.6.8 Receive Byte Counter (RBYT)
Figure 15-59 shows the RBYT register.
Offset eTSEC1:0x2_469C; eTSEC2:0x2_569C
0
R
W
Reset
Table 15-63 describes the fields of the RBYT register.
Bits Name
0–31 RBYT Receive byte counter. The statistic counter register increments by the byte count of frames received, including
those in bad packets, excluding preamble and SFD but including FCS bytes.
15.5.3.6.9 Receive Packet Counter (RPKT)
Figure 15-60 describes the definition for the RPKT register.
Offset eTSEC1:0x2_46A0; eTSEC2:0x2_56A0
0
R
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
9 10
Table 15-62. TRMGV Field Descriptions
Figure 15-59. Receive Byte Counter Register Definition
Table 15-63. RBYT Field Descriptions
9 10
—
Figure 15-60. Receive Packet Counter Register Definition
Enhanced Three-Speed Ethernet Controllers
TRMGV
All zeros
Description
RBYT
All zeros
Description
RPKT
All zeros
Access: Read/Write
31
Access: Read/Write
31
Access: Read/Write
31
15-83