Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 255

5.6.5.3 Periodic Interval Timer Prescale Register (PTPSR)
The periodic interval timer prescale register (PTPSR), shown in
used to configure the PIT prescaler's value.
Offset 0x08
0
R
W
Reset
Figure 5-35. Periodic Interval Timer Prescale Register (PTPSR)
Table 5-51 defines the bit fields of PTPSR.
Bits Name
0–31 PRSC PIT prescaler bits. Selects the input clock divider to generate the PIT counter clock. The prescaler is
programmed to divide the PIT clock input by values from 1 to 4,294,967,296. The value 0x0000 divides the
clock by 1 and 0xFFFF_FFFF divides the clock by 4,294,967,296.
To accurately predict the timing of the next count, change the PRSC bit only when the enable bit PTCNR[CLE]
is clear. Changing PRSC resets the prescaler counter. System reset and the loading of a new value into the
counter also reset the prescaler counter. Clearing the PTCNR[CLE] bit stops the prescaler counter.
5.6.5.4 Periodic Interval Timer Counter Register (PTCTR)
The periodic interval timer counter register (PTCTR), shown in
shows the current value in the PIT counter. The PTCTR counter is not affected by reads or writes.
Offset 0x0C
0
R
W
Reset
Figure 5-36. Periodic Interval Timer Counter Register (PTCTR)
Table 5-52 defines the bit fields of PTCTR.
Bits Name
0–31 CNTV PIT counter value field. Contains the current value of the time counter. This is a read-only field. Writes have
no effect on PTCTR[CNTV].
5.6.5.5 Periodic Interval Timer Event Register (PTEVR)
The periodic interval timer event register (PTEVR), shown in
the interrupts. The register can be read at any time.
PTEVR bits are cleared by writing ones. Writing zeros does not affect the value of the status bits.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
PRSC
All zeros
Table 5-51. PTPSR Bit Settings
Description
CNTV
All zeros
Table 5-52. PTCTR Bit Settings
Description
Figure 5-35, is a read/write register that
Figure 5-36, is a read-only register that
Figure 5-37, is used to report the source of
System Configuration
Access: Read/Write
31
Access: Read only
31
5-47