Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 188

Reset, Clocking, and Initialization
Table 4-21. Local Bus Reset Configuration Words Data Structure (continued)
EEPROM Address
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
4.3.3.1.1 Local Bus Controller Setting
The device will use GPCM to load the reset configuration from EEPROM or NOR Flash. The device will
read 64 bytes in this case. The local bus controller's registers setting will be set according to
The device will use FCM to load the reset configuration from NAND Flash. The device will read 512 bytes
if small size NAND Flash is used, or 2048 bytes if large page NAND Flash is used. The local bus
controller's registers setting will be set according to
The device will use PCI_SYNC_IN clock to generate the internal LCLK, which will run at half the
frequency of PCI_SYNC_IN.
CFG_RESET_SOURCE
0000
0001
0101
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-22
[0:7]
RCWL[16:23]
RCWL[24:31]
RCWH[0:7]
RCWH[8:15]
RCWH[16:23]
RCWH[24:31]
Table 4-22. Local Bus Controller Setting When Loading RCW
Meaning
NOR Flash
NAND Flash, 8 bit,
small page
NAND Flash, 8 bit,
large page
EEPROM Data Bits
[8:15] [16:23]
Table 4-22.
BR0[PS] BR0[MSEL]
10 000
01 001
01 001
[24:31]
Table
OR0[SCY] OR0[PGS]
1111 NA
0010 0
0010 1
Freescale Semiconductor
4-22.