Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 809

15.5.3.6.24 Receive Dropped Packet Counter (RDRP)
Figure 15-75 describes the definition for the RDRP register.
Offset eTSEC1:0x2_46DC; eTSEC2:0x2_56DC
0
R
W
Reset
Figure 15-75. Receive Dropped Packet Counter Register Definition
Table 15-79 describes the fields of the RDRP register.
Bits Name
0–15 — Reserved
16–31 RDRP Receive dropped packets counter. Increments for frames received which are streamed to system but
are later dropped due to lack of system resources.
15.5.3.6.25 Transmit Byte Counter (TBYT)
Figure 15-76 depicts the TBYT register.
Offset eTSEC1:0x2_46E0; eTSEC2:0x2_56E0
0
R
W
Reset
Table 15-80 describes the fields of the TBYT register.
Bits Name
0–31 TBYT Transmit byte counter. Increments by the number of bytes that were put on the wire including fragments of
frames that were involved with collisions. This count does not include preamble/SFD or jam bytes, except for
half-duplex flow control (back-pressure triggered by TCTRL[THDF] = 1). For THDF, the sum total of
'phantom' preamble bytes transmitted for flow control purposes is included in the TBYT increment value of
the next frame to be transmitted, up to 65,535 bytes of frame and phantom preamble.
Note that the value of TBYT may be greater than the actual number of bytes transmitted if the frame is
truncated because it exceeds MAXFRM.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
—
Table 15-79. RDRP Field Descriptions
Figure 15-76. Transmit Byte Counter Register Definition
Table 15-80. TBYT Field Descriptions
Enhanced Three-Speed Ethernet Controllers
15 16
All zeros
Description
TBYT
All zeros
Description
Access: Read/Write
RDRP
Access: Read/Write
15-91
31
31