Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 810

Enhanced Three-Speed Ethernet Controllers
15.5.3.6.26 Transmit Packet Counter (TPKT)
Figure 15-77 describes the definition for the TPKT register.
Offset eTSEC1:0x2_46E4; eTSEC2:0x2_56E4
0
R
W
Reset
Table 15-81 describes the fields of the TPKT register.
Bits Name
0–9 — Reserved
10–31 TPKT Transmit packet counter. Increments for each transmitted packet (including bad packets, excessive deferred
packets, excessive collision packets, late collision packets, all unicast, broadcast, and multicast packets).
15.5.3.6.27 Transmit Multicast Packet Counter (TMCA)
Figure 15-78 describes the definition for the TMCA register.
Offset eTSEC1:0x2_46E8; eTSEC2:0x2_56E8
0
R
W
Reset
Figure 15-78. Transmit Multicast Packet Counter Register Definition
Table 15-82 describes the fields of the TMCA register.
Bits Name
0–9 — Reserved
10–31 TMCA Transmit multicast packet counter. Increments for each multicast valid frame transmitted (excluding broadcast
frames) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
15-92
9 10
—
Figure 15-77. Transmit Packet Counter Register Definition
Table 15-81. TPKT Field Descriptions
9 10
—
Table 15-82. TMCA Field Descriptions
TPKT
All zeros
Description
TMCA
All zeros
Description
Access: Read/Write
31
Access: Read/Write
31
Freescale Semiconductor