Freescale Semiconductor PowerPC MPC823 Manuals

Manuals and User Guides for Freescale Semiconductor PowerPC MPC823. We have 1 Freescale Semiconductor PowerPC MPC823 manual available for free PDF download: Reference Manual

Freescale Semiconductor PowerPC MPC823 Reference Manual (1348 pages)

The Microprocessor for Mobile Computing

Brand: Freescale Semiconductor | Category: Computer Hardware | Size: 18 MB

Table of Contents
3
Introduction
49
Features
49
Architecture
54
The Embedded Powerpc Core
56
The System Interface Unit
56
The Communication Processor Module
57
The Video/Lcd Controller
58
The Video Controller
58
The LCD Controller
58
The PCMCIA-ATA Controller
58
Power Management
59
System Debug Support
59
Applications
59
Differences between Revisions a and B of the MPC823
59
MPC823 Glueless System Design
60
External Signals
61
The System Bus Signals
62
Signal Descriptions
62
Pin Breakout
73
Memory Map
76
MPC823 Internal Memory Map
76
Reset
88
Types of Reset
89
Power-On Reset
89
External Hard Reset
90
Internal Hard Reset
90
Loss of Lock
90
Software Watchdog Reset
90
Checkstop Reset
90
Debug Port Hard Reset
90
JTAG Reset
90
External Soft Reset
91
Internal Soft Reset
91
Debug Port Soft Reset
91
Reset Status Register
92
How to Configure Reset
94
Hard Reset
94
Hard Reset Configuration Word
97
Soft Reset
99
Clocks and Power Control
100
Features
100
Clocks and Power Control
101
Register Model
102
System Clock and Reset Control Register
102
PLL, Low-Power, and Reset Control Register
106
The Clock Module
109
On-Chip Oscillators and External Clock Input
111
System PLL
111
SPLL Stability
112
Power-On Reset Clock Configuration
112
The Low-Power Clock Divider
113
Internal Clock Signals
115
The General System Clocks
115
The Baud Rate Generator Clock
119
The Synchronization Clocks
119
The LCD Clocks
120
Clock Configuration
121
Mode Clock Pins
121
The System Phase-Locked Loop Pins
122
XFC Capacitor Values Based on the MF Field
122
Power Control
123
Power Rails
123
Power Switching Example
125
Key Registers
126
Low-Power Operation
127
MPC823 Low-Power Modes
130
The Powerpc Core
131
Features
131
Basic Structure of the Core
132
Instruction Flow Within the Core
132
Basic Instruction Pipeline
134
Sequencer Unit
134
Flow Control
135
Issuing Instructions
136
Interrupts
137
Implementing the Precise Exception Model
138
Restartability after an Interrupt
140
Processing an Interrupt
141
Serialization
142
Latency
142
The External Interrupt
143
Latency
143
Interrupt Ordering
144
The Register Unit
145
Control Registers
146
Physical Location of Special Registers
149
Machine State Register
150
The Condition Register
152
Fixed-Point Exception Cause Register
153
Initializing the Control Registers
154
System Reset Interrupt
154
Hard/Soft Reset
154
The Fixed-Point Unit
154
XER Update in Divide Instructions
154
The Load/Store Unit
155
Issuing Load/Store Instructions
156
Serializing Load/Store Instructions
157
Instructions Issued to the Data Cache
157
Issuing Store Instruction Cycles
157
Issuing Nonspeculative Load Instructions
157
Executing Unaligned Instructions
158
Little-Endian Mode Support
159
Atomic Update Primitives
159
Instruction Timing
160
Stalling Storage Control Instructions
160
Accessing Off-Core Special Registers
160
Storage Control Instructions
161
Exceptions
161
DAR, DSISR, and BAR Operation
161
Powerpc Architecture Compliance
162
Computation Modes
162
Reserved Fields
162
Classes of Instructions
162
Exceptions
163
The Branch Processor
163
Fetching Instructions
163
Branch Instructions
163
Branch Prediction
163
The Fixed-Point Processor
163
Move To/From System Register Instructions
163
The Load/Store Processor
164
Fixed-Point Load with Update and Store with
164
Optional Instructions
165
Powerpc Virtual Environment Architecture (Book II)
165
Storage Model
165
Memory Coherence
165
The Effect of Operand Placement on Performance
166
The Storage Control Instructions
166
Timebase
167
Powerpc Operating Environment Architecture (Book III)
167
The Branch Processor
167
The Fixed-Point Processor
167
Unsupported Registers
167
Added Registers
167
Storage Model
167
Address Translation
167
Reference and Change Bits
168
Storage Protection
168
Storage Control Instructions
168
Interrupts
168
Classes
168
Processing
168
Definitions
169
Alignment Interrupt
171
Program Interrupt
172
Trace Interrupt
172
Implementation-Dependent Software
173
Implementation-Specific Data TLB Miss
175
Implementation-Specific Data TLB Error
175
Instruction Execution Timing
179
Instruction Timing List
179
Instruction Execution Timing Examples
182
Data Cache Load
182
Writeback
183
Writeback Arbitration
183
Private Writeback Bus Load
184
Fastest External Load (Data Cache Miss)
185
A Full History Buffer
186
Branch Folding
187
Branch Prediction
188
Instruction Cache
189
Features
189
Programming the Instruction Cache
192
Instruction Cache Control and Status Register
193
Instruction Cache Address Register
194
Instruction Cache Data Port Register
195
Instruction Cache Operation
195
Instruction Cache Hit
195
Instruction Cache Miss
196
Instruction Fetch on a Predicted Path
196
Instruction Cache Commands
196
Invalidating the Instruction Cache
197
Loading and Locking the Instruction Cache
198
Unlocking a Line
198
Unlocking the Entire Instruction Cache
199
Inhibiting the Instruction Cache
199
Instruction Cache Read
200
Instruction Cache Write
202
Restrictions
202
Instruction Cache Coherency
202
Updating Code and Memory Region Attributes
202
Reset Sequence
202
Debug Support
202
Fetching Instructions from the Development Port
203
Data Cache
204
Copyback Mode
214
Writethrough Mode
215
Flushing and Invalidating the Cache
216
Enabling and Disabling the Cache
216
Locking and Unlocking the Cache
216
Dcbi, Dcbst, Dcbf and Dcbz Instructions
217
Memory Management Unit
218
Features
218
Address Translation
219
Translation Lookaside Buffer Operation
219
Protection
220
Storage Control
221
Translation Table Structure
222
Level One Descriptor
226
Level Two Descriptor
227
Programming the Memory Management Unit
232
Control Registers
233
MMU Instruction Control Register
233
MMU Data Control Register
234
MMU Current Address Space ID Register
235
MMU Instruction Effective Page Number Register
236
MMU Data Effective Page Number Register
237
MMU Instruction Real Page Number Register
238
MMU Data Real Page Number Register
243
MMU Instruction Access Protection Register
248
MMU Data Access Protection Register
249
MMU Instruction Tablewalk Control Register
250
MMU Data Tablewalk Control Register
251
MMU Tablewalk Base Register
253
MMU Tablewalk Special Register
254
MMU Data Content-Addressable Registers
254
MMU Data CAM Entry Read Register
255
MMU Data RAM Entry Read Register 0
256
MMU Data RAM Entry Read Register 1
258
MMU Instruction Content-Addressable Registers
260
MMU Instruction CAM Entry Read Register
260
MMU Instruction RAM Entry Read Register 0
262
MMU Instruction RAM Entry Read Register 1
263
Interrupts
264
Implementation-Specific Instruction TLB Miss
264
Implementation-Specific Data TLB Miss
264
Implementation-Specific Instruction TLB Error
265
Implementation-Specific Data TLB Error
265
Manipulating the Translation Lookaside Buffer
266
Reloading the Translation Lookaside Buffer
266
Translation Reload Examples
267
Controlling the TLB Replacement Counter
268
Invalidating the Translation Lookaside Buffer
268
Loading the Reserved TLB Entries
268
Requirements for Accessing the Memory Management Unit Control Registers
269
System Interface Unit
270
Features
271
System Configuration and Protection
271
Interrupt Configuration
274
The Interrupt Structure
274
Priority of the Interrupt Sources
275
Programming the Interrupt Controller
276
SIU Interrupt Pending Register
276
SIU Interrupt Mask Register
277
SIU Interrupt Edge/Level Register
278
SIU Interrupt Vector Register
279
The Bus Monitor
280
The Powerpc Decrementer
281
Decrementer Register
282
The Powerpc Timebase
283
Timebase Register
283
Timebase Reference Registers
284
Timebase Status and Control Register
285
The Real-Time Clock
286
Real-Time Clock Status and Control Register
287
Real-Time Clock Register
288
Real-Time Clock Alarm Seconds Register
289
Real-Time Clock Alarm Register
290
The Periodic Interrupt Timer
291
Periodic Interrupt Status and Control Register
292
Periodic Interrupt Timer Count Register
293
Periodic Interrupt Timer Register
294
The Software Watchdog Timer
295
Software Service Register
296
Freeze Operation
297
Low-Power Stop Operation
297
Multiplexing the System Interface Unit Pins
298
External Signals
298
Programming the System Interface Unit
299
System Configuration and Protection Registers
299
SIU Module Configuration Register
299
Internal Memory Map Register
303
System Protection Control Register
304
Transfer Error Status Register
305
External Bus Interface
307
Features
307
Transfer Signals
307
Control Signals
309
Bus Signal Descriptions
310
Bus Interface Operation
313
Basic Transfers
314
Single Beat Transfers
314
Single Beat Read Flow
315
Single Beat Write Flow
318
Burst Transfers
322
The Burst Mechanism
322
Transfer Alignment and Packaging
331
Arbitration Phase-Related Signals
333
Bus Request Signal
334
Bus Grant Signal
335
Bus Busy Signal
335
Address Transfer Phase-Related Signals
337
Transfer Start Signal
337
Address Bus
338
Transfer Attributes
338
Read/Write Signal
338
Burst Signal
338
Transfer Size Signal
339
Address Space Attributes
339
Special Transfer Start Signal
339
Burst Data in Progress Signal
342
Data Transfer Phase-Related Signals
342
Data Signal
342
Termination Phase-Related Signals
342
Transfer Acknowledge Signal
342
Burst Inhibit Signal
342
Transfer Error Acknowledge Signal
342
Protocol for Termination Signals
343
Storage Reservation Protocol
344
Exception Control Cycles
347
RETRY Signal
347
Endian Modes
352
Little-Endian Features
354
Big-Endian System Features
356
Powerpc Little-Endian System Features
356
Setting the Endian Mode of Operation
356
Memory Controller
357
Features
357
Architecture
360
Register Model
363
Register Descriptions
365
Base Registers
365
Memory Map
461

Freescale Semiconductor Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

More Freescale Semiconductor Manuals

Freescale Semiconductor PowerPC MPC823 Manuals

Freescale Semiconductor PowerPC MPC823 Reference Manual (1348 pages)

Table of Contents

Related Products

Freescale Semiconductor Categories