Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 548

Enhanced Local Bus Controller
LCLK
LAD
Address
LALE
A
TA
LA Row lsb's
LCS n
(RAS)
LBS n
(CAS)
LGPL1
(R/W)
LBCTL
cst1
cst2
cst3
cst4
bst1
bst2
bst3
bst4
g0l0
g0l1
g0h0
g0h1
g1t1
g1t3
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop
exen
amx0
amx1
na
uta
todt
last
Figure 10-77. Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-100
Address
Row
Column 1 lsb's
0
0
0 LALE
0
pause (due
1
to change
1
in AMX)
1
1
1
1
0
0
1
0
0
0
0
0
RBS RBS+1
Data 1
Column 1
0 0
0 0
0 0
0 0
1 0
1 0
1 0
0 0
1 1
1 1
1 1
0 1
0 0
0 0
0 1
0 1
0 0
0 0
RBS+2 RBS+3
Data 2
Column 2
Column 2 lsb's
1 Bit 0
1 Bit 1
1 Bit 2
1 Bit 3
1 Bit 4
1 Bit 5
1 Bit 6
1 Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
1 Bit 12
1 Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
0 Bit 24
0 Bit 25
0 Bit 26
0 Bit 27
0 Bit 28
0 Bit 29
1 Bit 30
1 Bit 31
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