Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 954

Universal Serial Bus Interface
16.3.2.13 Configure Flag Register (CONFIGFLAG)
This EHCI register is not used in this implementation. A read from this register returns a constant of a
0x0000_0001 to indicate that all port routings default to this host controller.
Offset 0x2_3180
31
R
W
Reset 0 0 0 0 0
Bits Name
31–1 — Reserved.
0 CF Configure flag. Always 1 indicating all port routings default to this host.
16.3.2.14 Port Status and Control Register (PORTSC)
The port status and control (PORTSC) register is only reset when power is initially applied or in response
to a controller reset. The initial conditions of a port are:
• No device connected
• Port disabled
If the port has port power control, this state remaivPns until software applies power to the port by setting
port power to one.
In device mode, the USB DR controller does not support power control. Port control in device mode is
only used for status port reset, suspend, and current connect status. It is also used to initiate test mode or
force signaling and allows software to put the PHY into low power suspend mode and disable the PHY
clock.
Offset 0x2_3184
31 30 29
R
PTS —
W
Reset 0 0 0
15 14 13
R
PIC PO
W
Reset
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
16-26
0 0 0 0 0 0 0 0
Figure 16-19. Configure Flag Register (CONFIGFLAG)
Table 16-22. CONFIGFLAG Register Field Descriptions
28 27 26 25
PSPD
— —
1 0 0 0
12 11 10 9
LS
PP —
Figure 16-20. Port Status and Control (PORTSC)
—
0 0 0 0 0 0 0 0
Description
24 23 22 21
PFSC PHCD WKOC WKDS WLCN
0 0 0
8 7 6
OCC
PR SUSP FPR
w1c
All zeros
Access: Read only
0 0 0 0 0 0 0
Access: Mixed
20 19
PTC
0 0 0 0
5 4 3 2
OCA PEC
PE
w1c
Freescale Semiconductor
1 0
CF
0 0 0 1
16
0 0
1 0
CSC CCS
w1c