Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 236

System Configuration
DDRCDR is shown in
Offset 0x00128
0 1
R
— DSO_EN
W
Reset 0 0
16
R
W
Reset
Table 5-31 shows the bit definition of the DDRCDR.
Bits Name
0 — Reserved
1 DSO_EN 0 DDR driver software override disable
1 DDR driver software override enable
2–5 DSO_PZ DDR driver software p-impedance override
0000 Half strength—Highest Z
1000 Much higher Z than nominal
1100 Higher Z than nominal
1110 Nominal impedance setting
1111 Lower Z than nominal
6–9 DSO_NZ DDR driver software n-impedance override
0000 Half strength—Highest Z
1000 Much higher Z than nominal
1100 Higher Z than nominal
1110 Nominal impedance setting
1111 Lower Z than nominal
10–11 — Reserved. Should be cleared.
12 ODT ODT termination value for I/Os
0 75 Ω
1 150 Ω
13 DDR_cfg Selects voltage level for DDR pads
0 DDR2 (1.8V mode) nominal impedance—18 Ω
1 DDR1 (2.5V mode) nominal impedance—18 Ω
Note: DDR_cfg must be set according to the logical type of the DDR memory devices, as it effects logic
14–29 — Reserved
30 M_odr Disable memory transaction reordering
0 Memory transaction reordering enabled
1 Memory transaction reordering disabled
31 Q_DRN 0 Drain queue before sleep disable
1 Drain queue before sleep enable
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
5-28
Figure 5-16.
2 5 6
DSO_PZ DSO_NZ
0 0 0 0 0 0
Figure 5-16. DDR Control Driver Register (DDRCDR)
Table 5-31. DDRCDR Field Descriptions
behavior of the DDR controller as well as the physical parameters of the DDR I/O pads.
9 10 11
—
0 0 0 0
—
All zeros
Description
Access: Read/Write
12 13 14
ODT DDR_cfg —
0 1 0
29 30
M_odr Q_DRN
Freescale Semiconductor
15
0
31