Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 367

8.5.2 System Global Interrupt Vector Register (SIVCR)
SIVCR, shown in Figure
source (INT) of the highest priority level.
Note that in core disabled mode the user should use SIVCR only in order to
read an updated interrupt vector (SCVCR and SMVCR should not be used).
Offset 0x04
0
R
IVECx
W
Reset
Table 8-5 defines the bit fields of SIVCR.
Bits Name
0–5 IVECx Backward (MPC8260) compatible regular interrupt vector. Specifies a 6-bit unique number of the IPIC's highest
priority regular interrupt source, pending to the core. When a regular interrupt request occurs, SIVCR can be
read. If there are multiple regular interrupt sources, SIVCR latches the highest priority regular interrupt. Note
that IVECx field correctly reflects only the first 64 interrupt vectors (See
The value of SIVEC cannot change while it is being read.
6–24 — Write ignored, read = 0
25–31 IVEC Regular interrupt vector. Specifies a 7-bit unique number of the IPIC's highest priority regular interrupt source,
pending to the core. Note that the when a regular interrupt request occurs, SIVCR can be read. If there are
multiple regular interrupt sources, SIVCR latches the highest priority regular interrupt. Note that the IVEC field
correctly reflects all interrupt vectors (see
The value of SIVCR cannot change while it is being read.
Table 8-6 shows the definition of IVEC.
Interrupt ID Number
0
1–8
9
10
11
12
13
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
8-3, contains a 7-bit code
5 6
Figure 8-3. System Global Interrupt Vector Register (SIVCR)
Table 8-5. SIVCR Field Descriptions
Table 8-6. IVEC/CVEC/MVEC Field Definition
Interrupt Meaning
Error (no interrupt)
Reserved
UART1
UART2
SEC
eTSEC1 1588 timer
eTSEC2 1588 timer
Integrated Programmable Interrupt Controller (IPIC)
(Table 8-5) representing the regular unmasked interrupt
NOTE
—
All zeros
Description
Table 8-6 for details).
0b000_0001–0b000_1000
Access: Read only
24 25
IVEC
Table 8-6 for details).
Interrupt Vector
0b000_0000
0b000_1001
0b000_1010
0b000_1011
0b000_1100
0b000_1101
31
8-9