Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 437

9.5.6 DDR SDRAM Registered DIMM Mode
To reduce loading, registered DRAM modules latch the DDR SDRAM control signals internally before
using them to access the array. Setting DDR_SDRAM_CFG[RD_EN] compensates for this delay on the
DRAM modules' control bus by delaying the data and data mask writes (on SDRAM buses) by an extra
SDRAM clock cycle.
Application system board must assert the reset signal on DDR memory
devices until software is able to program the DDR memory controller
configuration registers, and must deassert the reset signal on DDR memory
devices before DDR_SDRAM_CFG[MEM_EN] is set. This ensures that
the DDR memory devices are held in reset until a stable clock is provided
and, further, that a stable clock is provided before memory devices are
released from reset.
Figure 9-28 shows the registered DDR SDRAM DIMM single-beat write timing.
SDRAM Clock
MCS
MRAS
MCAS
MA n
MWE
MDQ n
MDQS
MDM[0:3]
Figure 9-28. Registered DDR SDRAM DIMM Burst Write Timing
9.5.7 DDR SDRAM Write Timing Adjustments
The DDR memory controller facilitates system design flexibility by providing a write timing adjustment
parameter, write data delay, (TIMING_CFG_2[WR_DATA_DELAY]) for data and DQS. The DDR
SDRAM specification requires DQS be received no sooner than 75% of an SDRAM clock period—and
no later than 125% of a clock period—from the capturing clock edge of the command/address at the
SDRAM. TIMING_CFG_2[WR_DATA_DELAY] specifies how much to delay the launching of DQS and
data from the first clock edge occurring one SDRAM clock cycle after the command is launched. The
delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
0 1 2 3 4
ACTTORW
ROW COL
NOTE
5 6 7 8
COL
D0 D1 D2 D3 D0
00
DDR Memory Controller
9 10 11 12
D1 D2 D3
9-43