Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 539

Local Bus Interface
10.5.2 Bus Turnaround
Because the local bus uses multiplexed address and data, special consideration must be given to avoid bus
contention at bus turnaround. The following cases must be examined:
• Address phase after previous read
• Read data phase after address phase
• Read-modify-write cycle for parity protected memory banks
• UPM cycles with additional address phases
The bus does not change direction for the following cases so they need no special attention:
• Continued burst after the first beat
• Write data phase after address phase
• Address phase after previous write
10.5.2.1 Address Phase after Previous Read
During a read cycle, the memory/peripheral drives the bus and the bus transceiver drives LAD. After the
data has been sampled, the output drivers of the external device must be disabled. This can take some time;
for slow devices the EHTR feature of the GPCM or the programmability of the UPM should be used to
guarantee that those devices have stopped driving the bus when the eLBC memory controller ends the bus
cycle.
In this case, after the previous cycle ends, LBCTL goes high and changes the direction of the bus
transceiver. The eLBC then inserts a bus turnaround cycle to avoid contention. The external device has
now already placed its data signals in high impedance and no bus contention will occur.
10.5.2.2 Read Data Phase after Address Phase
During the address phase, LAD actively drives the address and LBCTL is high, driving the bus
transceivers in the same direction as during a write. After the end of the address phase, LBCTL goes low
and changes the direction of the bus transceiver. The eLBC places the LAD signals in high impedance after
its t (LB). The LBCTL will have its new state after t
dis
the transceiver starts to drive those signals after its t
ensure, that [t (LB) + t
en
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
LAD[0:15]
LBCTL
Muxed Address/Data
Figure 10-73. GPCM Data Timings
(transceiver)] is larger than t
en
Buffer
Buffered Data
(LB) and, because this is an asynchronous input,
en
(transceiver) time. The system designer has to
en
(LB) to avoid bus contention.
dis
Enhanced Local Bus Controller
Slower
Device
Memories
Input
D
and
Pin
Peripherals
10-91