Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 807

15.5.3.6.20 Receive Undersize Packet Counter (RUND)
Figure 15-71 describes the definition for the RUND register.
Offset eTSEC1:0x2_46CC; eTSEC2:0x2_56CC
0
R
W
Reset
Figure 15-71. Receive Undersize Packet Counter Register Definition
Table 15-75 describes the fields of the RUND register.
Bits Name
0–15 — Reserved
16–31 RUND Receive undersize packet counter. Increments each time a frame is received which is less than 64 bytes in
length and contains a valid FCS and were otherwise well formed. This count does not include range length
errors.
15.5.3.6.21 Receive Oversize Packet Counter (ROVR)
Figure 15-72 describes the definition for the ROVR register.
Offset eTSEC1:0x2_46D0; eTSEC2:0x2_56D0
0
R
W
Reset
Figure 15-72. Receive Oversize Packet Counter Register Definition
Table 15-76 describes the fields of the ROVR register.
Bits Name
0–15 — Reserved
16–31 ROVR Receive oversize packet counter. Increments each time a frame is received which exceeded 1518 (non
VLAN) or 1522 (VLAN) and contains a valid FCS and was otherwise well formed.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
—
All zeros
Table 15-75. RUND Field Descriptions
—
All zeros
Table 15-76. ROVR Field Descriptions
Enhanced Three-Speed Ethernet Controllers
15 16
Description
15 16
Description
Access: Read/Write
RUND
Access: Read/Write
ROVR
15-89
31
31