Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 563

Offset
0x0_8218 DMADAR2—DMA 2 destination address register
0x0_8220 DMABCR2—DMA 2 byte count register
0x0_8224 DMANDAR2—DMA 2 next descriptor address register
0x0_8280 DMAMR3—DMA 3 mode register
0x0_8284 DMASR3—DMA 3 status register
0x0_8288 DMACDAR3—DMA 3 current descriptor address register
0x0_8290 DMASAR3—DMA 3 source address register
0x0_8298 DMADAR3—DMA 3 destination address register
0x0_82A0 DMABCR3—DMA 3 byte count register
0x0_82A4 DMANDAR3—DMA 3 next descriptor address register
0x0_82A8 DMAGSR—DMA general status register
0x0_82B0– Reserved
0x0_82FF
12.3 Register Descriptions
The following sections describe the DMA/messaging unit configuration, control, and status registers.
The registers described in this section use little-endian byte ordering.
Software running on the local processor in big-endian mode must byte-swap
the data. No byte swapping occurs when the registers are accessed from the
PCI bus.
12.3.1 Outbound Message Interrupt Status Register (OMISR)
OMISR contains the interrupt status of the doorbell and outbound message registers. A PCI device
acknowledges the outbound message interrupt by writing a 1 to the appropriate status bit: OMISR[OM1I]
or OMISR[OM0I]. Setting one of these bits clears both the interrupt and the corresponding status bit. The
local processor provokes an outbound message interrupt by writing to either of the two outbound message
registers: OMR0 or OMR1. OMISR can be accessed from the CSB or the PCI bus, but it is normally
accessed only from the PCI bus.
Offset 0x030
31
R
W
Reset
Figure 12-2. Outbound Message Interrupt Status Register (OMISR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table 12-1. Module Memory Map (continued)
Register
NOTE
Figure 12-2 shows the OMISR fields.
—
All zeros
DMA/Messaging Unit
Access Reset
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
— —
4 3
ODI
Section/Page
12.3.8.5/12-13
12.3.8.6/12-14
12.3.8.7/12-14
12.3.8.1/12-9
12.3.8.2/12-11
12.3.8.3/12-12
12.3.8.4/12-13
12.3.8.5/12-13
12.3.8.6/12-14
12.3.8.7/12-14
12.3.8.8/12-15
—
Access: Mixed
2 1 0
OM1I OM0I
—
w1c w1c
12-3