Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 481

10.3.1.16 Clock Ratio Register (LCRR)
The clock ratio register, shown in
provides configuration bits for extra delay cycles for address and control signals.
For proper operation of the system, it is required that this register setting
will not be altered while local bus memories or devices are being accessed.
Special care needs to be taken when running instructions from an eLBC
memory.
Offset 0x0_50D4
0
R
W
Reset 1 0 0 0 0
Table 10-23 describes LCRR fields.
Bits Name
0–13 — Reserved
14–15 EADC External address delay cycles of LCLK. Defines the number of cycles for the assertion of LALE.
00 4
01 1
10 2
11 3
16–26 — Reserved
27–31 CLKDIV System clock divider. Sets the frequency ratio between the system clock and the local bus clock. The
system clock is equivalent to csb_clk or twice csb_clk (if RCWL[LBIUCM] is set). Only the values shown
below are allowed.
Note: It is critical that no transactions are being executed via the local bus while CLKDIV is being
00000–00001 Reserved
00010 2
00011 Reserved
00100 4
00101–00111 Reserved
01000 8
01001–11111 Reserved
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Figure 10-20, sets the system clock to eLBC bus frequency ratio. It also
—
0 0 0 0 0 0 0 0
Figure 10-20. Clock Ratio Register (LCRR)
Table 10-23. LCRR Field Descriptions
modified. As such, prior to modification, the user must ensure that code is not executing out of the
local bus. Once LCRR[CLKDIV] is written, the register should be read, and then an isync should
be executed.
NOTE
13 14 15 16
EADC
0 0 0 0 0 0 0 0
Description
Enhanced Local Bus Controller
Access: Read/Write
26 27
— CLKDIV
n
0 0 0 0 0 0 0
30 31
n 0
0
10-33