Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 420

DDR Memory Controller
Table 9-17. Settings of DDR_SDRAM_MD_CNTL Fields (continued)
Field Mode Register Set
CS_SEL
MD_SEL Select mode register.
See Table 9-16
MD_VALUE Value written to mode
register
CKE_CNTL
9.4.1.12 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL)
The DDR SDRAM interval configuration register, shown in
cycles between bank refreshes issued to the DDR SDRAMs. In addition, the number of DRAM cycles that
a page is maintained after it is accessed is provided here.
Offset 0x124
0
R
W
Reset
Figure 9-13. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL)
Table 9-18 describes the DDR_SDRAM_INTERVAL fields.
Bits Name
0–15 REFINT Refresh interval. Represents the number of memory bus clock cycles between refresh cycles. Depending on
DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each DDR SDRAM physical bank
during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the interface
clock frequency. Refreshes are not issued when the REFINT is set to all 0s.
16–17 — Reserved
18–31 BSTOPRE Precharge interval. Sets the duration (in memory bus clocks) that a page is retained after a DDR SDRAM
access. If BSTOPRE is zero, the DDR memory controller uses auto-precharge read and write commands
rather than operating in page mode. This is called global auto-precharge mode.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
9-26
Refresh
Chooses chip select (CS)
—
.
—
0 0
REFINT
Table 9-18. DDR_SDRAM_INTERVAL Field Descriptions
Precharge
Selects logical bank
Only bit five is significant.
.
See Table 9-16
0
Figure 9-13, sets the number of DRAM clock
15 16 17 18
—
All zeros
Description
Clock Enable Signals
Control
—
—
—
.
See Table 9-16
Access: Read/Write
31
BSTOPRE
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