Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 200

Reset, Clocking, and Initialization
Table 4-28. Reset Status Register Field Descriptions (continued)
Bits Name
15 BSF Boot sequencer fail. If set, indicates that the I
configuration words. Cleared by writing a 1 to it (writing zero has no effect).
16–18 — Reserved, should be cleared.
19 SWHR Software hard reset. If set, indicates a software hard reset. SWHR is cleared by writing a 1 to it (writing
zero has no effect).
20–22 — Reserved, should be cleared.
23 JSRS JTAG soft reset status. Set when the JTAG reset request is set and remains set until software clears it.
JSRS is cleared by writing a 1 to it (writing zero has no effect).
0 No JTAG reset event.
1
24–26 — Reserved, should be cleared.
27 CSHR Check stop reset status. When the core enters a checkstop state and the checkstop reset is enabled by
the RMR[CSRE], CSRS is set and it remains set until software clears it. CSRS is cleared by writing a 1
to it (writing zero has no effect).
0 No enabled check stop reset event.
1 Enabled check stop reset event.
28 SWRS Software watchdog reset status. When a software watchdog expire event (which causes a reset) is
detected, SWRS is set and remains that way until the software clears it. SWRS is cleared by writing a
1 to it (writing zero has no effect).
0 No software watchdog reset event.
1 Software watchdog reset event.
29 BMRS Bus monitor reset status. When a bus monitor expire event (which causes a reset) is detected, BMRS
is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it (writing zero
has no effect).
0 No bus monitor reset event.
1 Bus monitor reset event.
30 — Reserved
31 HRS Hard reset status. When an external or internal hard reset event is detected, HRS is set and remains
set until software clears it. HRS is cleared by writing a 1 (writing zero has no effect).
0 No hard reset event.
1 Hard reset event.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
4-34
JTAG reset event.
Description
2
C boot sequencer has failed while loading the reset
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