Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 514

Enhanced Local Bus Controller
10.4.3.3.2 FCM Command, Address, and Write Data Timing
The FCM command (CM0–CM3, CW0, CW1), address (CA, PA, UA), and data write (WB, WS)
instructions all share the same basic timing attributes. Assertion of LFWE initiates transfer via LAD[0:7],
and the options in ORn for FCM mode establish the set-up, hold, and wait state timings with respect to
LFWE, as shown in Figure
LCLK
(unused)
LFCLE/
LFALE
LFWE
LAD[0:7]
TA
Notes:
Figure 10-51. Timing of FCM Command/Address and Write Data Cycles
The timing parameters are summarized in
Table 10-36. FCM Command, Address, and Write Data Timing Parameters
Option Register Attributes
TRLX CHT
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
1
In the parameters, SCY refers to a delay of OR n [SCY] clock cycles.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
10-66
10-51.
write cycle #1
t
WP
t
WS
t
CST
t
WC
command/address
t = Command to LFWE set-up time.
CST
t = Command to LFWE hold time.
CHT
t = Command/address to write data delay.
ADL
(for TRLX = 0, CHT = 0, CST = 1, SCY = 1, CLKDIV = 4*N)
Table
CST t
CST
0 0
1 ¼
0 0
1 ¼
0 ½
1 1
0 ½
1 1
t
ADL
t
CHT
t = LFWE pulse time, driven low.
WP
t = Command wait state time.
WS
t = Command cycle time.
WC
10-36.
Timing Parameter (LCLK Clock Cycles)
t t t
CHT WS
½ SCY 1½+SCY
½ SCY 1¼+SCY
1 SCY 1+SCY
1 SCY ¾+SCY
1½ 2×SCY 1+2×SCY
1½ 2×SCY ½+2×SCY
2 2×SCY ½+2×SCY
2 2×SCY 2×SCY
write cycle #2
write data
1
t t
WP WC ADL
2+SCY 4×(2+SCY)
2+SCY 4×(2+SCY)
2+SCY 4×(2+SCY)
2+SCY 4×(2+SCY)
3+2×SCY 8×(2+SCY)
3+2×SCY 8×(2+SCY)
3+2×SCY 8×(2+SCY)
3+2×SCY 8×(2+SCY)
Freescale Semiconductor