Freescale Semiconductor MPC8313E PowerQUICC II Pro Family Reference Manual page 287

5.8.3.6 Exiting Core and System Low Power States
The device can exit low power state and return to full-on mode for one of the following reasons:
• The core internal time base unit invokes a request to exit low power state.
• The core has received an interrupt request.
• The device is a PCI host, and the power management controller has detected that the system is not
idle and there are outstanding requests for transactions on the internal bus.
• The device is a PCI agent, and the power management controller has detected that the PCI power
next state does not equal the PCI power current state (meaning that the remote PCI host has
requested a change from non D0 to D0 state).
The actions taken to exit low power state depend on the mode and whether the system or only the core are
in this state. The following sections describe the various scenarios.
5.8.3.6.1 Exiting Low Power States—Core-Only Mode
Exit from Doze mode is controlled only by the core itself and does not involve the power management
controller or other blocks in the device. For a detailed description, see
Nap or Sleep modes are exited when the core has received an interrupt request, or according to the internal
time base unit of the core (Nap mode only). The source of the interrupt can be an internal block or external
signal. When the core returns to full-on state, it signals to the power management controller that it is ready
and is immediately acknowledged to access the rest of the system.
5.8.3.6.2 Exiting Low Power States—Core and System Mode
The power management controller decides to exit low power state when it detects that the system is not
idle anymore. The device may exit idle state when one of the peripheral interfaces makes a request to
access the internal bus or when the core returns to full-on state, as described above, and makes a request
to access the internal bus. For example, the TSEC receives an Ethernet frame, and requires to store it on
the DDR SDRAM memory.
If the DDR SDRAM memory controller is in low power state (PMCCR[DxLPEN] was set when entering
low power state), the power management controller initially enables the DDR SDRAM memory
controller. DDR SDRAM clocks (MCKn) are enabled and the memory controller exit self-refresh and
returns to auto-refresh mode.
The power management controller then enables other internal units and interrupts the PowerPC core.
When all internal units, including the core, are ready, the power management controller enables the device
to return to full-on state, negate the QUIESCE output, and clear PMCCR[SLPEN]. Outstanding requests
for transactions are now granted to execute on the internal bus.
Software is required to enable PMCI interrupt by setting PMCMR[PMCIE],
otherwise exiting from low power state is not possible.
It is the software's responsibility to clear PMCER[PMCI].
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
Table
NOTE
NOTE
System Configuration
7-1.
5-79